vivado与modelsim仿真不同原因？

在使用vivado仿真序列检测器时，发现波形与同一个testbench下单独用modelsim仿真出的波形存在区别。
（该序列检测器的序列为101011）

软件版本分别是modelsim se-64 10.4和vivado 2020.1
（vivado使用的编译器是modelsim）

源代码和testbench如下：

module sequential_detector
(clk,reset,x,y);
    input clk,reset,x;
    output y;
    reg y;
    reg[3:0] state,next_state;
    parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5,s6=4'd6;
    
    always @(posedge clk or posedge reset)
    begin
        if(reset==1)
            state <= s0;
        else
            state <= next_state;
    end
    
    always @(state or x)
    begin
        casex(state)
        s0:
            begin
                if(x==1)    begin next_state = s1;    y=0;end
                else    begin next_state = s0;    y=0;end
            end
        s1:
            begin
                if(x==0)    begin next_state = s2;    y=0;end
                else    begin next_state = s1;    y=0;end
            end
        s2:
            begin
                if(x==1)    begin next_state = s3;    y=0;end
                else    begin next_state = s0;    y=0;end
            end
        s3:
            begin
                if(x==0)    begin next_state = s4;    y=0;end
                else    begin next_state = s1;    y=0;end
            end
        s4:
            begin
                if(x==1)    begin next_state = s5;    y=0;end
                else    begin next_state = s0;    y=0;end
            end
        s5:
            begin
                if(x==1)    begin next_state = s6;    y=1;end
                else    begin next_state = s4;    y=0;end
            end
        s6:
            begin
                if(x==1)    begin next_state = s1;    y=0;end
                else    begin next_state = s2;    y=0;end
            end
        default:    next_state = s0;
        endcase
    end
endmodule

`timescale 1ns/1ns
module sequential_detector_tb();
    reg clk,reset,x;
    wire y;
    
    initial
        begin
            clk = 1;
        end
    
    always #5 clk = ~clk;
    
    always #5 reset = 0;
        
    initial
        begin
            x=1;
        
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=0;
            #10 x=1;
            #10    x=1;    //check 101011
            
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=1;    //check 10101011
            
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=1;
            
            #10    x=0;
            #10    x=1;
            #10    x=0;
            #10    x=1;
            #10    x=1;   //check 10101101011
            
            #10    $stop;
        end
    sequential_detector u(.x(x),.y(y),.clk(clk),.reset(reset));
endmodule        

第一次遇到这种问题，确实无从下手。

望能指点迷津。

只看代码，reset 的激励少了 1
从波形上看，reset 信号也不完整
在激励文件里面 initial 中，加上 reset = 1;