quartus 并置运算符求解！

任务：4个输入 Z_flag 、C_flag 、loadpsw 、loadpsw2 ； loadpsw为1把C_flag存到psw的低1位 ，loadpsw2为1 把Z_flag存到高1位 ，输出是1个2位psw

--------PSW---------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PSW IS
     PORT(
           RESET:in std_logic;
             CLK:in std_LOGIC;
             LoadPSW1:in std_LOGIC;
             LoadPSW2:in std_LOGIC;
             Z_flag:IN STD_LOGIC;
             C_flag:IN STD_LOGIC;
             c:out STD_LOGIC_vector(1 downto 0)
       );
END PSW;
ARCHITECTURE A OF PSW is 
signal Z_flagin,C_flagin:std_logic;

begin
    process(RESET,CLK,LoadPSW1,Z_flag,C_flag,LoadPSW2)
    begin
        if RESET='1' then
            c<='00';
        elsif clk'event and clk = '1' then
            if LoadPSW1= '1' then
                Z_flagin <= Z_flag;
            elsif LoadPSW2= '1' then
               C_flagin <= C_flag;
            end if;
        end if;
    
        c <= (Z_flagin) & (C_flagin);
    end process;
end architecture;