Error (10500): VHDL syntax error at vote7.vhd(10) near text ":="; expecting "(", or "'", or "."怎么搞啊

Error (10500): VHDL syntax error at vote7.vhd(10) near text ":="; expecting "(", or "'", or "."

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vote7 IS
PORT (A1,A2,A3,A4,A5,A6,A7: IN STD_LOGIC;
            Y:OUT STD_LOGIC);
END vote7;
ARCHITECTURE a OF vote7 IS
 BEGIN
  SUM:=0
  IF A1=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A2=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A3=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A4=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A5=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A6=' 1 ' THEN SUM:=SUM+1; END IF;
  IF A7=' 1 ' THEN SUM:=SUM+1; END IF;
  IF SUM>3 THEN Y<=' 1 '; 
  ELSE Y<=' 0 ';
  END IF;
 END PROCESS;
END;

你SUM变量的定义是不是有问题；
不应该是variable sum interger := 0;