用Verilog HDL语言编写程序

利用quartus 2编写
利用case语句实现四选一数据选择器。

波形仿真时endtime设置为50us，四个信号a、b、c、d分别为1 3 5 7的方波，输出out，信号选择s1、s2。

`timescale 1ns/1ns
module testbench_select;
reg        a,b,c,d;
reg        s1,s2;
wire    o;
parameter CLK_PERIOD        = 1000;    
initial    
begin
    a = 0;    b = 0;    c = 0;    d = 0;
end
always    a = #(CLK_PERIOD/1) ~a;
always    b = #(CLK_PERIOD/3) ~b;
always    c = #(CLK_PERIOD/5) ~c;
always    d = #(CLK_PERIOD/7) ~d;

initial    
begin
            s2 = 0;    s1 = 0;
    #10000    s2 = 0;    s1 = 1;
    #10000    s2 = 1;    s1 = 0;
    #10000    s2 = 1;    s1 = 1;
end

select    ux
(
    .a        (a),
    .b        (b),
    .c        (c),
    .d        (d),
    .s1        (s1),
    .s2        (s2),
    .o        (o)
);
endmodule

module select
(
    input    a,b,c,d,s1,s2,
    output    reg        o
);

always@(*)
begin
    case({s2,s1})
    2'b00:    o <= a;
    2'b01:    o <= b;
    2'b10:    o <= c;
    2'b11:    o <= d;
    endcase
end
endmodule