[Silk To Silk Clearance Constraint Violation] PCB1.PcbDoc Advanced PCB Silk To Silk Clearance Constraint: (7.424mil < 10mil) Between Text "+" (4667.283mil,3134.488mil) on Top Overlay And Track (4640mil,3090mil)(4740mil,3090mil) on Top Overlay Silk Text to Silk Clearance [7.425mil] 18:06:53 2022/8/23 9
不明白你在表达什么
你贴出来的报错是丝印间的间距调小,不满足你设置的规则,调整一下间距或者改下规则就好了