第一次用VHDL语言
编写的三个文件都是第一行出错误：
Error (10500): VHDL syntax error at clkin.vhd(1) near text "process"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at clk2,pin.vhd(1) near text "process"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at mclk.vhd(1) near text "process"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
这是什么错误啊
help www
也不知道你的文件内容，简直就不知道怎么回答。把我自己的HDL文件，前面的一点代码贴出来吧，你自己对应下：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.vid_edid_common_pkg.all;
-- entity declaration
entity vid_edid_rom is
generic (
gIIC_DEVICE_ADDRESS : unsigned (7 downto 1) := "1011100"; -- 0xb8,0xb9 by default
gIIC_DEVICE_PAGE_ADDRESS : unsigned (7 downto 1) := "1011100"; -- 0xb8,0xb9 by default
gROM_SIZE : integer := 128 -- size of the ROM in bytes
);
port (
-- control clock and reset
ctl_clk : in std_ulogic; -- clock to run internal logic
ctl_reset : in std_ulogic; -- ctl_clk synchronous reset, active low
-- rom array interface
kROM_BYTE_ARRAY : in tUNSIGNED8_ARRAY(0 to gROM_SIZE-1); -- ROM byte array
-- iic interface
iic_scl_in : in std_ulogic; -- serial clock input
iic_sda_in : in std_ulogic; -- serial data input
iic_sda_out : out std_ulogic -- data output
);
end entity vid_edid_rom;