用verilog 编写测量时间间隔的模块，误差小于0.01

module FrequencyCounter(
  input wire clk, // 输入时钟信号
  input wire signal, // 输入信号
  output reg [6:0] display[4:0] // 数码管输出
);

  reg [31:0] counter;
  reg [31:0] high_counter;
  reg [31:0] low_counter;
  reg [31:0] prev_counter;
  reg [31:0] prev_high_counter;
  reg [31:0] prev_low_counter;
  reg [31:0] time_counter;

  always @(posedge clk) begin
    // 计数器递增
    counter <= counter + 1;

    if (signal) begin
      high_counter <= high_counter + 1;
    end else begin
      low_counter <= low_counter + 1;
    end

    if (counter == 100000000) begin
      // 计数周期结束
      display <= calc_freq(counter, high_counter, low_counter); // 用来显示频率
      display[4] <= calc_duty(high_counter, low_counter); // 用来显示占空比

      // 计算时间间隔
      time_counter <= calc_time_interval(counter, prev_counter, high_counter, prev_high_counter);

      // 重置计数器
      prev_counter <= counter;
      prev_high_counter <= high_counter;
      prev_low_counter <= low_counter;
      counter <= 0;
      high_counter <= 0;
      low_counter <= 0;
    end
  end

  function calc_freq(input [31:0] counter, input [31:0] high_counter, input [31:0] low_counter) 
    output [6:0] freq;
    // 计算频率的逻辑
  endfunction

  function calc_duty(input [31:0] high_counter, input [31:0] low_counter) 
    output [6:0] duty;
    // 计算占空比的逻辑
  endfunction

  function calc_time_interval(input [31:0] counter, input [31:0] prev_counter, input [31:0] high_counter, input [31:0] prev_high_counter) 
    output [31:0] time_interval;
    // 计算时间间隔的逻辑
  endfunction

endmodulendmodule