如何用Quartus设计输入方波模块，频率模块，占空比模块等模块

module FrequencyCounter (
  input wire clk,          // 输入时钟信号
  input wire reset,        // 复位信号
  input wire cnt_enable,   // 计数使能信号
  output wire [31:0] count  // 输出频率计数值
);

  reg [31:0] count_reg;     // 频率计数寄存器

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      count_reg <= 32'd0;
    end else if (cnt_enable) begin
      count_reg <= count_reg + 1;
    end
  end

  assign count = count_reg;

endmodule

module SevenSegmentDisplay (
  input wire [31:0] frequency,    // 输入频率值
  output wire [6:0] segment_output // 数码管段选输出
);

  // 数码管段选值
  wire [3:0] segment_value;

  // 此处省略编码逻辑，根据输入的频率值生成各数码管段选值的逻辑电路

  assign segment_output = segment_value;

endmodule

module DutyCycleCalculator (
  input wire clk,                    // 输入时钟信号
  input wire reset,                  // 复位信号
  input wire signal_in,               // 输入信号
  output wire [31:0] frequency,       // 输出频率计数值
  output wire [31:0] high_duration,   // 输出高电平持续时间计数值
  output wire [31:0] low_duration     // 输出低电平持续时间计数值
);

  // 频率计数模块实例化
  FrequencyCounter counter (
    .clk(clk),
    .reset(reset),
    .cnt_enable(1'b1),
    .count(frequency)
  );

  reg [31:0] high_duration_reg;      // 高电平持续时间计数寄存器
  reg [31:0] low_duration_reg;       // 低电平持续时间计数寄存器
  reg last_signal_in;                // 上一次的信号输入值，用于判断信号的上升沿和下降沿

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      high_duration_reg <= 32'd0;
      low_duration_reg <= 32'd0;
      last_signal_in <= 1'b0;
    end else begin
      if (signal_in && !last_signal_in) begin
        // 上升沿
        high_duration_reg <= 32'd0;
      end else if (!signal_in && last_signal_in) begin
        // 下降沿
        low_duration_reg <= 32'd0;
      end

      if (signal_in) begin
        high_duration_reg <= high_duration_reg + 1;
      end else begin
        low_duration_reg <= low_duration_reg + 1;
      end

      last_signal_in <= signal_in;
    end
  end

  assign high_duration = high_duration_reg;
  assign low_duration = low_duration_reg;

endmodule

module TimeIntervalCalculator (
  input wire clk,                           // 输入时钟信号
  input wire reset,                         // 复位信号
  input wire signal_in_A,                    // 输入信号A
  input wire signal_in_B,                    // 输入信号B
  output wire [31:0] interval_duration       // 输出时间间隔计数值
);

  // 频率计数模块实例化
  FrequencyCounter counter (
    .clk(clk),
    .reset(reset),
    .cnt_enable(1'b1),
    .count(interval_duration)
  );

  reg last_signal_in_A;                       // 上一次信号A输入值，用于判断信号A的上升沿和下降沿
  reg last_signal_in_B;                       // 上一次信号B输入值，用于判断信号B的上升沿和下降沿
  reg [31:0] interval_duration_reg;            // 时间间隔计数寄存器
  reg [31:0] last_counter_value;               // 上一次频率计数器的计数值

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      interval_duration_reg <= 32'd0;
      last_signal_in_A <= 1'b0;
      last_signal_in_B <= 1'b0;
    end else begin
      if (signal_in_A && !last_signal_in_A && signal_in_B && !last_signal_in_B) begin
        // 两个输入信号同时上升沿
        interval_duration_reg <= counter;
      end else if (signal_in_A && !last_signal_in_A) begin
        // 信号A上升沿，保存此时的频率计数值
        last_counter_value <= counter;
      end else if (signal_in_B && !last_signal_in_B) begin
        // 信号B上升沿，计算时间间隔
        interval_duration_reg <= counter - last_counter_value;
      end

      last_signal_in_A <= signal_in_A;
      last_signal_in_B <= signal_in_B;
    end
  end

  assign interval_duration = interval_duration_reg;

endmodule