在编译DefaultFPGAConfig时出错，配置如下
class BaseConfig extends Config(
new WithDefaultMemPort() ++
new WithDefaultMMIOPort() ++
new WithDefaultSlavePort() ++
new WithTimebase(BigInt(1000000)) ++ // 1 MHz
new WithDTS("freechips,rocketchip-unknown", Nil) ++
new WithNExtTopInterrupts(2) ++
new BaseSubsystemConfig()
)
class BaseFPGAConfig extends Config(new BaseConfig ++ new WithCoherentBusTopology)
class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig)
在sims/verilator下make的报错信息如下
[info] running chipyard.Generator --target-dir /home/hmy/chipyard/sims/verilator/generated-src/chipyard.TestHarness.DefaultFPGAConfig --name chipyard.TestHarness.DefaultFPGAConfig --top-module chipyard.TestHarness --legacy-configs chipyard:DefaultFPGAConfig
[error] (run-main-0) java.lang.reflect.InvocationTargetException
[error] java.lang.reflect.InvocationTargetException
[error] at ... ()
[error] at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
[error] at ... ()
[error] at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
[error] Caused by: java.lang.IllegalArgumentException: requirement failed: Subsystem asyncClockGroups must be undriven
[error] at scala.Predef$.require(Predef.scala:281)
[error] at chipyard.clocking.HasChipyardPRCI.$init$(HasChipyardPRCI.scala:30)
[error] at chipyard.DigitalTop.<init>(DigitalTop.scala:15)
[error] at chipyard.BuildSystem$$anonfun$$lessinit$greater$1.apply(ChipTop.scala:16)
[error] at chipyard.BuildSystem$$anonfun$$lessinit$greater$1.apply(ChipTop.scala:16)
[error] at chipyard.ChipTop.lazySystem$lzycompute(ChipTop.scala:28)
[error] at chipyard.ChipTop.lazySystem(ChipTop.scala:28)
[error] at chipyard.TestHarness.<init>(TestHarness.scala:98)
[error] at java.base/jdk.internal.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
[error] at java.base/jdk.internal.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
[error] at java.base/jdk.internal.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
[error] at java.base/java.lang.reflect.Constructor.newInstance(Constructor.java:490)
[error] at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
[error] at chisel3.Module$.do_apply(Module.scala:53)
[error] at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:33)
[error] at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:719)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error] at chisel3.internal.Builder$.build(Builder.scala:714)
[error] at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:33)
[error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:245)
[error] at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error] at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error] at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:245)
[error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:242)
[error] at scala.collection.AbstractTraversable.flatMap(Traversable.scala:108)
[error] at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28)
[error] at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error] at firrtl.options.Translator.transform(Phase.scala:248)
[error] at firrtl.options.Translator.transform$(Phase.scala:248)
[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error] at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error] at firrtl.Utils$.time(Utils.scala:181)
[error] at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error] at scala.collection.immutable.List.foldLeft(List.scala:89)
[error] at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error] at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error] at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error] at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
[error] at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error] at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error] at firrtl.options.Translator.transform(Phase.scala:248)
[error] at firrtl.options.Translator.transform$(Phase.scala:248)
[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error] at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error] at scala.collection.immutable.List.foldLeft(List.scala:89)
[error] at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error] at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error] at logger.Logger$.makeScope(Logger.scala:135)
[error] at firrtl.options.Stage.transform(Stage.scala:47)
[error] at firrtl.options.Stage.transform(Stage.scala:17)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error] at firrtl.options.Translator.transform(Phase.scala:248)
[error] at firrtl.options.Translator.transform$(Phase.scala:248)
[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error] at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
[error] at firrtl.Utils$.time(Utils.scala:181)
[error] at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error] at scala.collection.immutable.List.foldLeft(List.scala:89)
[error] at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
[error] at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
[error] at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
[error] at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
[error] at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error] at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
[error] at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
[error] at firrtl.options.Translator.transform(Phase.scala:248)
[error] at firrtl.options.Translator.transform$(Phase.scala:248)
[error] at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
[error] at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
[error] at scala.collection.immutable.List.foldLeft(List.scala:89)
[error] at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
[error] at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
[error] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[error] at logger.Logger$.makeScope(Logger.scala:135)
[error] at firrtl.options.Stage.transform(Stage.scala:47)
[error] at firrtl.options.Stage.execute(Stage.scala:58)
[error] at firrtl.options.StageMain.main(Stage.scala:71)
[error] at chipyard.Generator.main(Generator.scala)
[error] at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
[error] at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
[error] at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
[error] at java.base/java.lang.reflect.Method.invoke(Method.java:566)
[error] stack trace is suppressed; run last Compile / bgRunMain for the full output
[error] Nonzero exit code: 1
[error] (Compile / runMain) Nonzero exit code: 1
[error] Total time: 15 s, completed Jun 15, 2023, 5:59:40 AM
/home/hmy/chipyard/common.mk:110: recipe for target 'generator_temp' failed
make: *** [generator_temp] Error 1
请问log中提到的报错“Subsystem asyncClockGroups must be undriven”是什么原因呢，应该如何解决
题外话：
说实话一直没有搞清楚这三个Config文件之间的关系
chipyard/generators/chipyard/src/main/scala/config/RocketConfig.scala
chipyard/generators/rocket-chip/src/main/scala/subsystem/Config.scala
chipyard/generators/rocket-chip/src/main/scala/system/Config.scala
但目前尝试下来感觉第一个RocketConfig.scala是顶层文件，里面的config可以被直接调用；
subsystem/Config.scala中的config需要在RocketConfig.scala中申明才能被调用；
system/Config.scala中的config目前好像没法调用成功，有点困惑、
可参考GPT的回答：
关于报错“Subsystem asyncClockGroups must be undriven”，它的意思是asyncClockGroups子系统必须是未连接的状态，但当前的配置中它被连接了。这可能是由于配置文件中的某些参数设置不正确导致的。
解决方法可能需要检查asyncClockGroups子系统的连接状态以及其他相关参数的设置，确保它们与所需的配置相匹配。
关于三个Config文件的关系，RocketConfig.scala是Chipyard的顶层配置文件，它包含了所有的默认配置和可选配置，可以被其他配置文件调用。subsystem/Config.scala是Rocket Chip中子系统的配置文件，它定义了子系统的默认配置和可选配置，可以在RocketConfig.scala中被调用。system/Config.scala是Rocket Chip中系统的配置文件，它定义了系统的默认配置和可选配置，也可以在RocketConfig.scala中被调用。在使用时，可以通过继承这些配置文件来实现自定义配置。
chipyard环境下仿真risc-v教程（1）：运行chipyard中的默认案例
案例可以参考下
https://blog.csdn.net/bxdzyhx/article/details/117969179
你提供的错误中指示了一个IllegalArgumentException错误，这个错误是常见的参数错误，Subsystem asyncClockGroups must be undrive的意思就是子系统中 DefaultFPGAConfig 中有一个叫做 asyncClockGroups 的属性没有被正确设置。因此，需要检查下DefaultFPGAConfig的配置中是否设置了asyncClockGroups 属性，或者是否设置正确。
检查硬件电路的定义，并确保所有时钟域都被正确连接