自适应中值滤波仿真结果正常，上板后不对图片进行处理（FPGA）

再做一个基于串口传图的自适应中值滤波项目（FPGA），实现过程中，单独实现窗口为（3x3、5x5）中值滤波仿真上板都是可以的，自适应中值仿真结果也是正常的，例化到顶层模块后上板，没有对图片进行处理。
使用的Verliog。求在线指导一下（有藏）

module adap_median_filter#(
    parameter DATA_WIDTH = 8
)(
    input wire sys_clk                  ,
    input wire rst_n                    ,
    input wire data_in_valid            ,
    input wire data_in_hs               ,
    input wire data_in_vs               ,
    input wire [DATA_WIDTH-1:0] data_in ,

    output wire data_out_hs             ,
    output wire data_out_vs             ,
    output wire [DATA_WIDTH-1:0]data_out,
    output wire data_out_valid          
    );

//S内部最大值、中值、最小值、中心点值
wire [DATA_WIDTH-1:0] S5_max,S5_med,S5_min;
wire [DATA_WIDTH-1:0] S3_max,S3_med,S3_min;//3x3模版输出中值（data_out）

wire [2:0] S    ;   //窗口模版尺寸

//wire [DATA_WIDTH-1:0] dout3_xy;
wire [DATA_WIDTH-1:0] dout5_xy;

wire m3_dout_valid;
wire m3_dout_hs;
wire m3_dout_vs;
wire m5_dout_valid;
wire m5_dout_hs;
wire m5_dout_vs;

//======= 5x5 Generate begin ========

wire [DATA_WIDTH-1:0] l0_data;    //第一行数据
wire [DATA_WIDTH-1:0] l1_data;
wire [DATA_WIDTH-1:0] l2_data;
wire [DATA_WIDTH-1:0] l3_data;
wire [DATA_WIDTH-1:0] l4_data;


shift_reg_5x5 shift_reg_5x5_u(
    .taps_clk     (sys_clk     ),
    .shift_in     (data_in     ),
    .shiftin_valid(data_in_valid),
    .shift_out    (    ),
    .taps3x       (l3_data       ),
    .taps2x       (l2_data       ),
    .taps1x       (l1_data       ),
    .taps0x       (l0_data       ) 
    );
assign l4_data = data_in;
//======= 5x5 Generate end ========

//======= adaptive logical begin ========
wire ws;
wire [DATA_WIDTH - 1 : 0] out3, out5;
assign ws = ((S3_min == S3_med)) || (S3_med == S3_max) ? 1 : 0;
assign out3 = ((dout5_xy == S3_min) || (dout5_xy == S3_max)) ? S3_med : dout5_xy;
assign out5 = ((dout5_xy == S5_min) || (dout5_xy == S5_max)) ? S5_med : dout5_xy;
assign data_out = ws ? out5 : out3;
//======= adaptive logical end ========

assign data_out_valid = (S==3)? m3_dout_valid:m5_dout_valid;
assign data_out_hs = (S==3)? m3_dout_hs:m5_dout_hs;
assign data_out_vs = (S==3)? m3_dout_vs:m5_dout_vs;

median_top #(
    .DATA_WIDTH(8)
)
median_top_u (
    .clk           (sys_clk       ),
    .rst_n         (rst_n         ),
    .l0_data       (l1_data       ),
    .l1_data       (l2_data       ),
    .l2_data       (l3_data       ),
    .data_in_valid (data_in_valid ),
    .data_in_hs    (data_in_hs    ),
    .data_in_vs    (data_in_vs    ),
    .data_out_min  (S3_min        ),
    .data_out_med  (S3_med        ),
    .data_out_max  (S3_max        ),
    .dout3_xy      (dout3_xy      ),
    .data_out_valid(m3_dout_valid ),
    .data_out_hs   (m3_dout_hs    ),
    .data_out_vs   (m3_dout_vs    )
    );

median_filter_5 #(
    .DATA_WIDTH( 8)
)
median_filter_5_u (
    .clk           (sys_clk       )  ,
    .reset_p       (!rst_n        )  ,
    .l0_data       (l0_data)    ,
    .l1_data       (l1_data)   ,     
    .l2_data       (l2_data)   ,     
    .l3_data       (l3_data)   ,     
    .l4_data       (l4_data)   ,     
    .data_in_valid (data_in_valid )  ,
    .data_in_hs    (data_in_hs    )  ,
    .data_in_vs    (data_in_vs    )  ,
    .data_out_min  (S5_min  )  ,
    .data_out_med  (S5_med  )  ,
    .data_out_max  (S5_max  )  ,
    .dout5_xy      (dout5_xy),
    .data_out_valid(m5_dout_valid)  ,
    .data_out_hs   (m5_dout_hs   )  ,
    .data_out_vs   (m5_dout_vs   )    
    );

endmodule

针对这些问题，你可以逐一排查，检查串口通信是否正常、FPGA逻辑是否正确、时序关系是否正确以及电源和时钟是否正常。如果无法确定问题所在，可以考虑使用仿真工具进行调试，或者借助示波器等硬件工具对电路进行调试。