VHDL时序电路逻辑设计

1．用 VHDL 语言设计实现一个分频系数为 10，分频输出信号占空比为 50%
的分频器，仿真验证设计。
2．用 VHDL 语言设计实现一个带异步复位的 8421 码十进制计数器，仿真验
证其功能。
3．将分频器、计数器和数码管译码器 3 个电路进行连接，实现一个每秒加 1
的计数器，并在数码管上显示计数结果。

需要修改代码，以满足题目要求
allproject部分

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY allproject IS
PORT(

     clear2 :IN STD_LOGIC;
     clk1:IN STD_LOGIC;
     b1:OUT STD_LOGIC_VECTOR(6 downto 0);
     CAT:OUT STD_LOGIC_VECTOR(7 downto 0)
);
end allproject;
ARCHITECTURE a OF allproject IS
COMPONENT div_10 
PORT(
     clk :IN STD_LOGIC; 
     clk_out:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT count10
PORT(
     clk,reset:IN STD_LOGIC;
     q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT seg7_1  
PORT(
     a:IN STD_LOGIC_VECTOR(3 downto 0);
     b:OUT STD_LOGIC_VECTOR(6 downto 0)
);
END COMPONENT;
SIGNAL na:STD_LOGIC;
SIGNAL nb:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
u1:div_10 PORT MAP(clk_out=>na,clk=>clk1);
u2:count10 PORT MAP(reset=>clear2,clk=>na,q=>nb);
u3:seg7_1 PORT MAP(a=>nb,b=>b1);
CAT<="11111101";
END a;

计数器count10部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count10 IS
PORT(
clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END count10;
ARCHITECTURE a OF count10 IS
SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk,reset)
BEGIN
IF reset='0' THEN
q_temp<="0000";
ELSIF clk'EVENT AND clk='1' THEN
IF q_temp="1001" THEN
q_temp<="0000";
ELSE q_temp<=q_temp+1;
END IF;
END IF;
END PROCESS;
q<= q_temp;
END a;

分频器div__10部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div_10 IS
PORT(
     clk :IN STD_LOGIC;
     clk_out:OUT STD_LOGIC;
      clear : IN STD_LOGIC
      );
END div_10;
ARCHITECTURE a OF div_10 IS
SIGNAL tmp:INTEGER RANGE 0 TO 4;
SIGNAL clktmp:STD_LOGIC;
BEGIN
PROCESS(clear,clk)
BEGIN
IF clk'event AND clk='1' THEN
   IF tmp = 4 THEN
      tmp<=0;clktmp<=NOT clktmp;
   ELSE 
      tmp <=tmp+1;
   END IF;
END IF;

END PROCESS;
clk_out<=clktmp;
END a;

数码管seg7_1部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY seg7_1 IS 
    PORT (
       a: IN STD_LOGIC_VECTOR(3 downto 0);
       b: OUT STD_LOGIC_VECTOR(6 downto 0);
       cat:out std_logic_vector(5 downto 0)
    );
 end seg7_1;
 ARCHITECTURE seg7_1_arch OF seg7_1 IS 
 BEGIN 
        PROCESS ( a ) 
        BEGIN 
           CASE a IS 
              WHEN "0000" => b <="1111110"; --0
              WHEN "0001" => b <="0110000"; --1
              WHEN "0010" => b <="1101101"; --2
              WHEN "0011" => b <="1111001"; --3
              WHEN "0100" => b <="0110011"; --4
              WHEN "0101" => b <="1011011"; --5
              WHEN "0110" => b <="1011111"; --6
              WHEN "0111" => b <="1110000"; --7
              WHEN "1000" => b <="1111111"; --8
              WHEN "1001" => b <="1111011"; --9
              WHEN OTHERS => b <="0000000"; 
           END CASE;
    END PROCESS; 
    cat<="111101";
 END;

最好能达到这样的仿真效果

引用chatGPT作答，以下是已修改的代码，已经添加了对题目要求的支持：

allproject部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY allproject IS
PORT(
clear2 :IN STD_LOGIC;
clk1:IN STD_LOGIC;
b1:OUT STD_LOGIC_VECTOR(6 downto 0);
CAT:OUT STD_LOGIC_VECTOR(7 downto 0)
);
end allproject;

ARCHITECTURE a OF allproject IS
COMPONENT div_10
PORT(
clk :IN STD_LOGIC;
clk_out:OUT STD_LOGIC
);
END COMPONENT;

COMPONENT count10
PORT(
clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;

COMPONENT seg7_1
PORT(
a:IN STD_LOGIC_VECTOR(3 downto 0);
b:OUT STD_LOGIC_VECTOR(6 downto 0)
);
END COMPONENT;

SIGNAL na:STD_LOGIC;
SIGNAL nb:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cnt: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
u1:div_10 PORT MAP(clk_out=>na,clk=>clk1);
u2:count10 PORT MAP(reset=>clear2,clk=>na,q=>nb);
u3:seg7_1 PORT MAP(a=>nb,b=>b1);
CAT <= "11111101";
PROCESS(clk1)
BEGIN
IF (rising_edge(clk1)) THEN
IF cnt = "1001" THEN
cnt <= "0000";
ELSE
cnt <= cnt + 1;
END IF;
END IF;
END PROCESS;

END a;

计数器count10部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count10 IS
PORT(
clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END count10;

ARCHITECTURE a OF count10 IS
SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
PROCESS(clk,reset)
BEGIN
IF reset = '0' THEN
q_temp <= "0000";
ELSIF (rising_edge(clk)) THEN
IF q_temp = "1001" THEN
q_temp <= "0000";
ELSE
q_temp <= q_temp + 1;
END IF;
END IF;
END PROCESS;
q <= q_temp;

END a;

分频器div__10部分

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div_10 IS
PORT(
clk :IN STD_LOGIC;
clk_out:OUT STD_LOGIC;
clear : IN STD_LOGIC
);
END div_10;

ARCHITECTURE a OF div_10 IS
SIGNAL tmp: INTEGER RANGE 0 TO 4;
SIGNAL clktmp: STD_LOGIC;
BEGIN
PROCESS(clear,clk)
BEGIN
IF (rising_edge(clk)) THEN
IF tmp = 4 THEN
tmp <= 0;
clktmp <= NOT clktmp;
ELSE
tmp <= tmp + 1;
END IF;
END IF;
END PROCESS;
clk_out <= clktmp;
END a;

数码管seg7_1部分

LIBRARY IEEE;
USE
IEEE.STD_LOGIC_1164.ALL;

ENTITY seg7_1 IS
PORT (
a: IN STD_LOGIC_VECTOR(3 downto 0);
b: OUT STD_LOGIC_VECTOR(6 downto 0);
cat: OUT STD_LOGIC_VECTOR(5 downto 0)
);
END seg7_1;

ARCHITECTURE seg7_1_arch OF seg7_1 IS
BEGIN
PROCESS (a)
BEGIN
CASE a IS
WHEN "0000" => b <= "1111110"; --0
WHEN "0001" => b <= "0110000"; --1
WHEN "0010" => b <= "1101101"; --2
WHEN "0011" => b <= "1111001"; --3
WHEN "0100" => b <= "0110011"; --4
WHEN "0101" => b <= "1011011"; --5
WHEN "0110" => b <= "1011111"; --6
WHEN "0111" => b <= "1110000"; --7
WHEN "1000" => b <= "1111111"; --8
WHEN "1001" => b <= "1111011"; --9
WHEN OTHERS => b <= "0000000";
END CASE;
END PROCESS;
cat <= "111101";
END seg7_1_arch;

```vb.net
library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_UNSIGNED.ALL;  
  
entity allproject is  
    Port (  
        clear2: in STD_LOGIC;  
        clk1: in STD_LOGIC;  
        b1: out STD_LOGIC_VECTOR(6 downto 0);  
        CAT: out STD_LOGIC_VECTOR(7 downto 0);  
    );  
end allproject;  
  
architecture Behavioral of allproject is  
    signal clear2: std_logic;  
    signal clk1: std_logic;  
    signal b1: std_logic_vector(6 downto 0);  
    signal CAT: std_logic_vector(7 downto 0);  
  
    Component div_10  
    Port (  
        clk: in std_logic;  
        clk_out: out std_logic  
    );  
end Component;  
  
Component count10  
    Port (  
        clk, reset: in std_logic;  
        q: out std_logic_vector(3 downto 0)  
    );  
end Component;  
  
Component seg7_1  
    Port (  
        a: in std_logic_vector(3 downto 0);  
        b: out STD_LOGIC_VECTOR(6 downto 0)  
    );  
end Component;  
  
Signal na: std_logic;  
Signal nb: std_logic_vector(3 downto 0);  
  
begin  
    u1: div_10 Port Map (clk_out=>na, clk=>clk1);  
    u2: count10 Port Map (reset=>clear2, clk=>na, q=>nb);  
    u3: seg7_1 Port Map (a=>a, b=>CAT);  
end Behavioral;

```

1. 分频器设计：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity freq_divider is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end freq_divider;

architecture Behavioral of freq_divider is
signal cnt: integer := 0;
signal temp_q: std_logic := '0';
begin
process (clk, rst)
begin
    if rst = '1' then
        cnt <= 0;
        temp_q <= '0';
    elsif rising_edge(clk) then
        if cnt = 9 then
            cnt <= 0;
            temp_q <= NOT temp_q;
        else
            cnt <= cnt + 1;
        end if;
    end if;
end process;
q <= temp_q;
end Behavioral;

2. 8421 码十进制计数器设计：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_counter is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           bcd_out : out  STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter;

architecture Behavioral of bcd_counter is
signal cnt: integer := 0;
begin
process (clk, rst)
begin
    if rst = '1' then
        cnt <= 0;
    elsif rising_edge(clk) then
        if cnt = 9 then
            cnt <= 0;
        else
            cnt <= cnt + 1;
        end if;
    end if;
end process;
bcd_out <= std_logic_vector(to_unsigned(cnt, 4));
end Behavioral;

3. 连接分频器、计数器和数码管译码器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (6 downto 0));
end main;

architecture Behavioral of main is
component freq_divider
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end component;

component bcd_counter
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           bcd_out : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

signal div_clk: std_logic;
signal bcd_out:_vector(3 downto 0);

begin
    divider: freq_divider
        port map (clk, rst, div_clk);
        
    counter: bcd_counter
        port map (div_clk, rst, bcd_out);
        
    process (bcd_out)
    variable temp: std_logic_vector(6 downto 0);
    begin
        case bcd_out is
            when "0000" => temp := "1000000";
            when "0001" => temp := "1111001";
            when "0010" => temp := "0100100";
            when "0011" => temp := "0110000";
            when "0100" => temp := "0011001";
            when "0101" => temp := "0010010";
            when "0110" => temp := "0000010";
            when "0111" => temp := "1111000";
            when "1000" => temp := "0000000";
            when "1001" => temp := "0010000";
            when others => temp := "1111111";
        end case;
        seg <= temp;
    end process;
end Behavioral;

I