板子第一次烧录程序报错,具体报错类容如图
OIProject 1-4791 Netlist was created with Vivado 2018.3
O IProject 1-570] Preparing netlist for logic optimization
O [Timing 38-478] Restoring timing data from binary archive.
i[Timing 38-479]Binary timing data restore complete
OIProject 1-856]Restoring constraints from binary archive
0 IProject 1-8531 Binary constraint restore complete
>O ITiming 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. (1 more like this)
O[Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
O [Labtools 27-2222] Launching hw_server.
OLabtools 27-2221]Launch Output
****** Xilinx hw_server V2018.3
****Build date:Dec72018-00:40:27
** Copyright 1986-2018 Xilinx,Inc.AlI Rights Reserved.
O ILabtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210251A08870
O[Labtools 27-1435] Device Xc7a35t (JTAG device index =0)is not programmed (DONE status = 0)
_** VO [Labtools 27-3165]End of startup status: LOW(1 more like this)
O[Labtools 27-3165]End of startup status:LOW__**_
望采纳
这个错误可能是由于你的FPGA芯片的电源电压不足导致的,你可以检查一下FPGA芯片的电源电压是否符合要求,如果不符合要求,可以尝试更换电源电压,或者检查一下FPGA芯片的连接是否正确。