描述jk触发器功能的vhdl语言有错误

求问这个描述jk触发器的vhdl语言哪里出错了😭
library ieEe;
use ieEe.std_logic_1164.all;
use ieEe.std_logic_unsigned.all;
use ieEe.std_logic_arith.all;
entity jk1 is
port(j,k,clk:in std_logic;
q,nq:buffer std_logic);
end jk1;
architecture bh of jk1 is
begin
process(clk)
begin
if falling_edge(clk) then
if j='0'and k='1'then
q<='0';
nq<='1';
else if j='1'and k='0'then
q<='1';
nq<='0';
else if j='1'and k='1'then
q<=not q;
nq<=not nq;
else if j='0'and k='0'then
q<=q;
nq<=nq;
end if;
end if;
end process;
end bh;