怎么用神经网络实现二输入与、或、异或操作呢？用的是Verilog语言，要求用神经网络。用的开发板是FPGA的AX301
可参考这篇免费博文操作https://blog.csdn.net/weixin_43942325/article/details/97896578?ops_request_misc=&request_id=&biz_id=102&utm_term=verilog%E7%A5%9E%E7%BB%8F%E7%BD%91%E7%BB%9C%E4%BA%8C%E8%BE%93%E5%85%A5&utm_medium=distribute.pc_search_result.none-task-blog-2~blog~sobaiduweb~default-4-97896578.nonecase&spm=1018.2226.3001.4450