verilog重复例化一个模块，使其并行进行计算，无法布线，布线报错。

以下是demo程序，重复例化两个模块

chnl_sel u0_chnl_sel(
    .i_clk        (wr_clk),
    .i_rst_n     (sys_rst_n),
    .chnl_init     (CHN_NUM0_INIT_ADDR),
    .ch_emifa_cs_n (cs_n),        // EMIFA chip-select, active low               
    .ch_emifa_oe_n (oe_n),        // EMIFA output enable, active low.            
    .ch_emifa_we_n (we_n),        // EMIFA write enable, active low.             
    .ch_emifa_addr (addr),        // EMIFA Address                          
    .ch_emifa_data (data_chn0)    
    );
chnl_sel u1_chnl_sel(
    .i_clk        (wr_clk),
    .i_rst_n     (sys_rst_n),
    .chnl_init     (CHN_NUM0_INIT_ADDR),
    .ch_emifa_cs_n (cs_n),        // EMIFA chip-select, active low               
    .ch_emifa_oe_n (oe_n),        // EMIFA output enable, active low.            
    .ch_emifa_we_n (we_n),        // EMIFA write enable, active low.             
    .ch_emifa_addr (addr),        // EMIFA Address                          
    .ch_emifa_data (data_chn1)    
    );

编译器给出的错误：
[Place 30-99] Placer failed with error: 'There are more instances than sites for type STARTUP'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

代码不全，无法判断

就给几个顶层例化，看得出啥东西喔