Verilog如何实现在某特定边沿触发开始计数？

问题遇到的现象和发生背景

想实现在信号A的上升沿处开始触发，此刻信号B拉高电平，计数器计数到30240时，信号B电平拉低，计数器清0。相当于信号B高电平持续时间为30240个时钟周期。

问题相关代码，请勿粘贴截图

reg o_rdy1_temp1;
reg o_rdy1_temp2;
wire spadbuffer_out_trigger;
always @(posedge clk)
begin
    if(asy_rst_n)
    begin
        o_rdy1_temp1 <= 1'b0;
        o_rdy1_temp2 <= 1'b0;
    end
    else begin
        o_rdy1_temp1 <= o_rdy1;
        o_rdy1_temp2 <= o_rdy1_temp1;
    end
end
assign spadbuffer_out_trigger = o_rdy1_temp1 & (~o_rdy1_temp2);    //信号A的上升沿
reg spadbuffer_out_trigger_reg;                                                             //将上升沿锁存起来 
wire spadbuffer_out_en;
reg spadbuffer_out_en_reg;
reg [14:0] cnt_30240;
always @(posedge clk)
begin
    if(asy_rst_n)
    begin
        spadbuffer_out_en_reg <= 1'd0;
        cnt_30240 <= 15'd0;
    end
    else
    begin
        spadbuffer_out_trigger_reg <= spadbuffer_out_trigger;
    end

    if(spadbuffer_out_trigger_reg)
    begin
        cnt_30240 <= cnt_30240 + 15'd1;
        spadbuffer_out_en_reg <= spadbuffer_out_en_reg + 1'd1;
    end
    else if(cnt_30240 == 15'd30240)
    begin
        cnt_30240 <= 15'd0;
        spadbuffer_out_en_reg <= 1'd0;                
    end
    else
    begin
        cnt_30240 <= cnt_30240 + 15'd1;
        spadbuffer_out_en_reg <= spadbuffer_out_en_reg + 1'd1;
    end    
end
assign spadbuffer_out_en = spadbuffer_out_en_reg;

运行结果及报错内容

我的解答思路和尝试过的方法

通过边沿检测，已经检测到A信号的上升沿，但是由于其上升沿只有一个时钟周期，无法作为计数器的使能信号，所以想求解一下如何得到信号B

我想要达到的结果

reg o_rdy1_temp1;
reg o_rdy1_temp2;
wire spadbuffer_out_trigger;
always @(posedge clk)
begin
    if(asy_rst_n)
    begin
        o_rdy1_temp1 <= 1'b0;
        o_rdy1_temp2 <= 1'b0;
    end
    else begin
        o_rdy1_temp1 <= o_rdy1;
        o_rdy1_temp2 <= o_rdy1_temp1;
    end
end
assign spadbuffer_out_trigger = o_rdy1_temp1 & (~o_rdy1_temp2);    //信号A的上升沿
reg spadbuffer_out_trigger_reg;                                                             //将上升沿锁存起来 
wire spadbuffer_out_en;
reg spadbuffer_out_en_reg;
reg [14:0] cnt_30240 = 15'h7fff;

always @(posedge clk)
begin
    if(asy_rst_n)
    begin
        spadbuffer_out_trigger_reg <= 1'd0;
    end
    else
    begin
        spadbuffer_out_trigger_reg <= spadbuffer_out_trigger;
    end
end

always @(posedge clk)
begin
    if(asy_rst_n)
    begin
        cnt_30240 <= 15'h7fff;
        spadbuffer_out_en_reg <= 1'd0;
    end
    if(spadbuffer_out_trigger_reg)
    begin
        cnt_30240 <= 15'd0;
        spadbuffer_out_en_reg <= 1'd1;
    end
    else if(cnt_30240 < 15'd30240)
    begin
        cnt_30240 <= cnt_30240 + 15'd1;
        spadbuffer_out_en_reg <= 1'd1;                
    end
    else
    begin
        spadbuffer_out_en_reg <= 0;
    end    
end
assign spadbuffer_out_en = spadbuffer_out_en_reg;
    

你先把语法bug解决。再仿真看看。