verilog程序报错

这段程序实现的是计算输入位中为1的个数并赋值给输出
module top_module(
input [2:0] in,
output [1:0] out );
assign out=2'b0;
genvar i;
generate
for(i=0;i<3;i=i+1)begin:x
if(in[i]==1)begin
out=out+1;
end
end
endgenerate
endmodule
然后报错在
Error (10170): Verilog HDL syntax error at top_module.v(9) near text: "="; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.3327919/top_module.v Line: 9
Error (10112): Ignored design unit "top_module" at top_module.v(1) due to previous errors File: /home/h/work/hdlbits.3327919/top_module.v Line: 1
麻烦解答一下 谢谢！

module top_module
(
    input    [2:0]    in,
    output    [1:0]    out 
);
reg        out_r = 0;
assign    out    = out_r;
genvar i;
generate
always@(in)
begin
    for(i=0;i<3;i=i+1)
    begin:x
        out_r = out_r + in[i];
    end
end
endgenerate
endmodule