module count_odd
(input clk,reset,N,output cout);
reg m,n; reg cout1,cout2;
assign cout=cout1|cout2;
always @(posedge clk)
begin if(!reset) begin cout1<=0;m<=0;end
else
begin if(m==N-1) m<=0;else m<=m+1;
if(m<(N-1)/2) cout1<=1;else cout1<=0;
end end
always @(negedge clk)
begin if(!reset) begin cout2<=0;n<=0;end
else begin
if(n==N-1) n<=0;else n<=n+1;
if(n<(N-1)/2) cout2<=1;else cout2<=0;end
end
endmodule
module count_even
(input clk,reset,N,output reg cout);
reg m;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin m<=0;cout<=0;end
else if(m==N-1)
begin m<=0;cout<=~cout;end
else
begin m<=m+1;end
end
endmodule
module count_dec
(input clk,reset,N,output reg cout);
reg cout1,cout2;
always @(posedge clk,posedge reset)
begin if(reset)begin cout1<=0;cout2<=0;cout<=0;end
else if(cout1<9)
begin
if(cout2<(N/10)-1)begin cout2<=cout2+1;cout<=0;end
else begin cout2<=0;cout1<=cout1+1;cout<=1;end
end
else
begin
if(cout2<N-9*(N/10)-1) begin cout2<=cout2+1;cout<=0;end
else begin cout2<=0;cout1<=cout1+1;cout<=1;end
end
end
endmodule
module count (
input clk,reset,
input N,
output cout
);
reg [1:0] a;
always @*
begin
if( N%2==0&&N%1==0)
begin
a<=2'b00;
end
else if(N%2==1&&N%1==0)
begin
a<=2'b01;
end
else
begin
a<=2'b10;
end
end
always@(a)
begin
case(a)
2'b00: count_even(.clk(clk),.reset(reset),.N(N),.cout(cout));
2'b01: count_odd(.clk(clk),.reset(reset),.N(N),.cout(cout));
default: count_even(.clk(clk),.reset(reset),.N(N),.cout(cout));
endcase
end
endmodule
tb
module count_tb();
reg clk,reset,N;
wire cout;
count i1(
.clk(clk),
.reset(reset),
.N(N),
.cout(cout)
);
parameter DELY=20;
always
begin
clk=1;
#(DELY) clk<=~clk;
end
initial
begin
N<=8;reset<=1;
#(DELY*10)N=11;
#(DELY*10)N=8.1;
#(DELY*10) $stop;
end
endmodule
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
[VRFC 10-2989] 'count_even' is not declared ["D:/5e/count/count.srcs/sources_1/new/count.v":96]
[XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
[VRFC 10-2989] 'count_odd' is not declared ["D:/5e/count/count.srcs/sources_1/new/count.v":97]
[VRFC 10-2989] 'count_even' is not declared ["D:/5e/count/count.srcs/sources_1/new/count.v":98]
######最开始是用if-else语句
if( N%2==0&&N%1==0)
begin
count_even(.clk(clk),.reset(reset),.N(N),.cout(cout));
end
else if(N%2==1&&N%1==0)
begin
count_odd(.clk(clk),.reset(reset),.N(N),.cout(cout));
end
else
begin
count_even(.clk(clk),.reset(reset),.N(N),.cout(cout));
end
后来问了才知道 Verilog 好像识别不了这种写法 换了种写法 发现没有（错误波浪线）以为case语句可以用
后来仿真还是仿真不了出错误
verilog 是硬件描述语言。你还是没有理解例化的含义。这不是软件通过变量选择调用什么样的函数。
例化一个模块，相当于在电路板上焊上一个芯片。一块板子需要焊什么芯片是根据设计需求，电路设计决定的。我们使用时板子上的芯片就已经焊好了。不会因为某个变量的变化，新焊上一个芯片或动态拆掉一个芯片。
verilog 是硬件描述语言就是在描述在 fpga 内部放置一个什么样的芯片，这个芯片是什么逻辑，怎么接线。
举个例子，设计一款声光报警器。聋子来了就闪光报警，瞎子来了就声音报警器。我们不能只例化了一个声音或发光模块，要将这两个模块都例化才行。根据某个变量来决定是发声还是发光。
你需要将奇偶分频器都例化，会有两个频率输出，通过 N 去选择哪个频率输出就行。
module count (
input clk,reset,
input N,
output reg cout
);
reg [1:0] a;
wire cout_o,cout_e;
count_even even1(.clk(clk),.reset(reset),.N(N),.cout(cout_e));
count_odd odd1(.clk(clk),.reset(reset),.N(N),.cout(cout_o));
always @(*)
begin
if( N%2==0&&N%1==0)
begin
a<=2'b00;
end
else if(N%2==1&&N%1==0)
begin
a<=2'b01;
end
else
begin
a<=2'b10;
end
end
always@(a)
begin
case(a)
2'b00: cout=cout_e;
2'b01: cout=cout_o;
default: cout=cout_e;
endcase
end
endmodule
你这是条件例化语法错误。
1条件例化的条件必须是常数。if case 都必须是常数
2不能在 always 中例化