verilog中在做44矩阵键盘,用八个数码管显示按键值,显示延迟一次按键

问题遇到的现象和发生背景

题目为:将按键值显示在7端数码管上,并在数码管上完成显示键值的移动,例如第一次按键“1”,数码管显示“1”,第二次按键“2”,数码管显示“12”,
我的代码:在按下1后不显示,在按下2后显示1,在按下三后显示2,也就是显示上次按键

问题相关代码,请勿粘贴截图

行已上拉电阻

module juzhenjianpan(row,col,clk,reset,led,pian);
//行:row 列:col
input clk,reset;
input [3:0] row;
output [3:0] col;
output [7:0] led;
output [2:0] pian;
reg[3:0] col;
reg[3:0] row_reg,col_reg;
reg clk2; //分频用clk2
reg [5:0] count=0;//10计数表示20ms的延迟
reg [2:0] state=0;
reg[3:0] key_value;
reg[2:0] pian=3'b111;
reg [7:0] led;
reg [7:0] led0;
reg [0:0] panduan;
reg [7:0]seg[7:0];
reg flag;

always @(posedge clk)
begin

    if(count>=10)
    begin
        clk2<=~clk2;
        count<=0;
    end
    else count<=count+1;
end 

always @ (*)
begin
if(!reset) begin led0=8'b00000000;end
else begin
    case(key_value)
            0: led0=8'b11111100;
            1: led0=8'b01100000;
            2: led0=8'b11011010;
            3: led0=8'b11110010;
            4: led0=8'b01100110;
            5: led0=8'b10110110;
            6: led0=8'b10111110;
            7: led0=8'b11100000;
            8: led0=8'b11111110;
            9: led0=8'b11110110;
            10: led0=8'b11101110;
            11: led0=8'b00111110;
            12: led0=8'b10011100;
            13: led0=8'b01111010;
            14: led0=8'b10011110;
            15: led0=8'b10001110;
        default:led0=8'b00000000;
    endcase
     end
end

always @(posedge clk2)
begin
    if(!reset) begin col<=4'b0000;
                    seg[0][7:0]=8'b00000000;
                    seg[1][7:0]=8'b00000000;
                    seg[2][7:0]=8'b00000000;
                    seg[3][7:0]=8'b00000000;
                    seg[4][7:0]=8'b00000000;
                    seg[5][7:0]=8'b00000000;
                    seg[6][7:0]=8'b00000000;
                    seg[7][7:0]=8'b00000000;
                  end
    else
    begin
        case(state)
            0:begin
                col<=4'b0000;                 //检测是否有按键按下,当有按下跳入1中,否则一直扫描
                panduan<=0;
                flag<=1;
                if(row!=4'b1111)
                begin
                    state<=1;
                    col<=4'b1110;
                end
                else state<=0;
              end
            
            1:begin
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else begin state<=2;
                        col<=4'b1101;
                        end
              end
              
            2:begin
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else begin
                            state<=3;
                            col<=4'b1011;
                        end
              end
            
            3:begin
                if(row!=4'b1111)
                begin
                 state<=5;
                end
                else begin 
                        state<=4;
                        col<=4'b0111;
                      end
              end
              
            4:begin
                col<=4'b0111;
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else state<=0;
              end
            5:begin
                if(row!=4'b1111)
                begin
                    col_reg<=col;
                    row_reg<=row;
                    panduan<=1;
                    state<=5;
                end
                else begin
                    state<=0;
                end
              end
        endcase
        
        
        case ({col_reg,row_reg})

                    8'b1110_1110:key_value=10;
                    8'b1110_1101:key_value=11;
                    8'b1110_1011:key_value=12;
                    8'b1110_0111:key_value=13;                    
                    8'b1101_1110:key_value=3;
                    8'b1101_1101:key_value=6;                    
                          8'b1101_1011:key_value=9;
                    8'b1101_0111:key_value=15;
                    8'b1011_1110:key_value=2;
                    8'b1011_1101:key_value=5;
                          8'b1011_1011:key_value=8;
                    8'b1011_0111:key_value=0;
                    8'b0111_1110:key_value=1;
                          8'b0111_1101:key_value=4;
                    8'b0111_1011:key_value=7;
                    8'b0111_0111:key_value=14;     
       endcase
    end
     if(panduan&&flag)
     begin
     seg[0][7:0]<=led0;
     seg[1][7:0]<=led0;
     seg[2][7:0]<=seg[1][7:0];
     seg[3][7:0]<=seg[2][7:0];
     seg[4][7:0]<=seg[3][7:0];
     seg[5][7:0]<=seg[4][7:0];
     seg[6][7:0]<=seg[5][7:0];
     seg[7][7:0]<=seg[6][7:0];
     panduan<=1;
     flag<=0;
     end
end

always @ (posedge clk)
begin
    if(!reset) 
    begin led=8'b00000000;
    end
    else
    begin
    pian=pian-1;
    led=seg[pian][7:0];
    end  
end


endmodule 

运行结果及报错内容
我的解答思路和尝试过的方法

我认为出错的原因在于阻塞和非阻塞赋值,但是并没有解决

我想要达到的结果

按键不再延迟显示



module juzhenjianpan(row,col,clk,reset,led,pian);
//行:row 列:col
input clk,reset;
input [3:0] row;
output [3:0] col;
output [7:0] led;
output [2:0] pian;
reg[3:0] col;
reg[3:0] row_reg,col_reg;
reg clk2; //分频用clk2
reg [5:0] count=0;//10计数表示20ms的延迟
reg [2:0] state=0;
reg[3:0] key_value;
reg[2:0] pian=3'b111;
reg [7:0] led;
reg [7:0] led0;
reg [0:0] panduan;
reg [7:0]seg[7:0];
reg flag;
always @(posedge clk)
begin
    if(count>=10)
    begin
        clk2<=~clk2;
        count<=0;
    end
    else count<=count+1;
end 
always @ (*)
begin
if(!reset) begin led0=8'b00000000;end
else begin
    case(key_value)
            0: led0=8'b11111100;
            1: led0=8'b01100000;
            2: led0=8'b11011010;
            3: led0=8'b11110010;
            4: led0=8'b01100110;
            5: led0=8'b10110110;
            6: led0=8'b10111110;
            7: led0=8'b11100000;
            8: led0=8'b11111110;
            9: led0=8'b11110110;
            10: led0=8'b11101110;
            11: led0=8'b00111110;
            12: led0=8'b10011100;
            13: led0=8'b01111010;
            14: led0=8'b10011110;
            15: led0=8'b10001110;
        default:led0=8'b00000000;
    endcase
     end
end
always @(posedge clk2)
begin
    if(!reset) begin col<=4'b0000;
                    seg[0][7:0]=8'b00000000;
                    seg[1][7:0]=8'b00000000;
                    seg[2][7:0]=8'b00000000;
                    seg[3][7:0]=8'b00000000;
                    seg[4][7:0]=8'b00000000;
                    seg[5][7:0]=8'b00000000;
                    seg[6][7:0]=8'b00000000;
                    seg[7][7:0]=8'b00000000;
                  end
    else
    begin
        case(state)
            0:begin
                col<=4'b0000;                 //检测是否有按键按下,当有按下跳入1中,否则一直扫描
                panduan<=0;
                flag<=1;
                if(row!=4'b1111)
                begin
                    state<=1;
                    col<=4'b1110;
                end
                else state<=0;
              end
            1:begin
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else begin state<=2;
                        col<=4'b1101;
                        end
              end
            2:begin
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else begin
                            state<=3;
                            col<=4'b1011;
                        end
              end
            3:begin
                if(row!=4'b1111)
                begin
                 state<=5;
                end
                else begin 
                        state<=4;
                        col<=4'b0111;
                      end
              end
            4:begin
                col<=4'b0111;
                if(row!=4'b1111)
                begin
                    state<=5;
                end
                else state<=0;
              end
            5:begin
                if(row!=4'b1111)
                begin
                    col_reg<=col;
                    row_reg<=row;
                    panduan<=1;
                    state<=5;
                end
                else begin
                    state<=0;
                end
              end
        endcase
        
//        case ({col_reg,row_reg})
//                    8'b1110_1110:key_value=10;
//                    8'b1110_1101:key_value=11;
//                    8'b1110_1011:key_value=12;
//                    8'b1110_0111:key_value=13;                    
//                    8'b1101_1110:key_value=3;
//                    8'b1101_1101:key_value=6;                    
//                          8'b1101_1011:key_value=9;
//                    8'b1101_0111:key_value=15;
//                    8'b1011_1110:key_value=2;
//                    8'b1011_1101:key_value=5;
//                          8'b1011_1011:key_value=8;
//                    8'b1011_0111:key_value=0;
//                    8'b0111_1110:key_value=1;
//                          8'b0111_1101:key_value=4;
//                    8'b0111_1011:key_value=7;
//                    8'b0111_0111:key_value=14;     
//       endcase
    end
     if(panduan&&flag)
     begin
     seg[0][7:0]<=led0;
     seg[1][7:0]<=led0;
     seg[2][7:0]<=seg[1][7:0];
     seg[3][7:0]<=seg[2][7:0];
     seg[4][7:0]<=seg[3][7:0];
     seg[5][7:0]<=seg[4][7:0];
     seg[6][7:0]<=seg[5][7:0];
     seg[7][7:0]<=seg[6][7:0];
     panduan<=1;
     flag<=0;
     end
end
always @ (posedge clk)
begin
    if(!reset) 
    begin led=8'b00000000;
    end
    else
    begin
    pian=pian-1;
    led=seg[pian][7:0];
    end  
end

always @(posedge clk)
begin
    if(!reset) 
    begin
        key_value = 0;
    end
    else
    begin
        case ({col_reg,row_reg})
        8'b1110_1110:key_value=10;
        8'b1110_1101:key_value=11;
        8'b1110_1011:key_value=12;
        8'b1110_0111:key_value=13;                    
        8'b1101_1110:key_value=3;
        8'b1101_1101:key_value=6;                    
        8'b1101_1011:key_value=9;
        8'b1101_0111:key_value=15;
        8'b1011_1110:key_value=2;
        8'b1011_1101:key_value=5;
        8'b1011_1011:key_value=8;
        8'b1011_0111:key_value=0;
        8'b0111_1110:key_value=1;
        8'b0111_1101:key_value=4;
        8'b0111_1011:key_value=7;
        8'b0111_0111:key_value=14;     
        endcase
    end
end

endmodule