数字逻辑设计题目，可以帮忙解答一下吗，谢谢！

作出“101”序列信号检测器的状态表，凡收到输入序列101时，输出就为1，并规定检测的101序列不重叠。，如x=010101101，z=

```c
module SerialSequenceDetector(
    input d,
     input rst_n,
    input clk,
    output   flag
    );

reg [1:0] CurrentSequence ;

parameter Sequence=3'd101;

always @(posedge clk)
    begin
        if(!rst)
            begin
                CurrentSequence <= 0;
            end
        else
            begin
                if(flag)
                    CurrentSequence <= 0
                else
                    CurrentSequence <= {CurrentSequence[1:0],din};
            end
    end
    
    assign flag = (CurrentSequence == Sequence)?1'b1:1'b0;

```