菜鸟编程，Verilog语言编程中仿真没有计算，代码是这样的，不知道哪里出了问题

module xs(
clk,
en,
rst,
rect,
new,
xy,
ratioX,
ratioY,
Index00,
Index01,
Index10,
Index11,
IntY,
IntX,
SrcY,
SrcX
);
input[25:0] rect,new,xy;
input clk,en,rst;
output[25:0] Index00,Index01,Index10,Index11;
output [12:0] IntY,IntX,SrcY,SrcX,ratioY,ratioX;
reg [25:0] Index00,Index01,Index10,Index11;
reg [12:0] IntY,IntX,SrcY,SrcX,ratioY,ratioX;
reg[1:0] i;
always @(posedge clk)
begin
if(!rst)
begin
Index00<=13'd0;
Index01<=13'd0;
Index10<=13'd0;
Index11<=13'd0;
IntY <= 13'd0;
IntX <= 13'd0;
SrcX <= 13'd0;
SrcY <= 13'd0;
ratioX <=13'd0;
ratioY <=13'd0;
end
else
if(!en)
begin
ratioY <=13'd100*(rect[12:0]-1) / (new[12:0]-1);
ratioX <=13'd100*(rect[25:13]-1) / (new[25:13]-1);
IntY <= xy[12:0]*13'd100*ratioY>>13'd100;
IntX <= xy[25:13]* 13'd100*ratioX>>13'd100;
SrcY <= IntY + 13'd1;
SrcX <= IntX + 13'd1;
Index00 <= {IntX,IntY};
Index01 <= {IntX,SrcY};
Index10 <= {SrcX,IntY};
Index11 <= {SrcX,SrcY};
end
end
endmodule