Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

MODELSIM SE 仿真实现不了

错误代码为Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

激励和初始值都已经赋予

代码如下

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER16B_vhd_tst IS
END ADDER16B_vhd_tst;
ARCHITECTURE ADDER16B_arch OF ADDER16B_vhd_tst IS
-- constants

-- signals

COMPONENT ADDER16B
PORT (
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CIN : IN STD_LOGIC;
COUT : OUT STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
SIGNAL A1:STD_LOGIC_VECTOR(15 DOWNTO 0):="1111000011110000";
SIGNAL B1:STD_LOGIC_VECTOR(15 DOWNTO 0):="1111000011110000";
SIGNAL CIN1:STD_LOGIC:= '0';
SIGNAL COUT1:STD_LOGIC:='1';
SIGNAL DOUT1:STD_LOGIC_VECTOR(15 DOWNTO 0):="1111000011110000";
CONSTANT CLK_P : TIME:=200 NS;
BEGIN
i1 : ADDER16B
PORT MAP (
-- list connections between master ports and signals
A => A1,
B => B1,
CIN => CIN1,
COUT => COUT1,
DOUT => DOUT1
);
PROCESS

-- variable declarations

BEGIN
CIN1<='0'; WAIT FOR CLK_P;
CIN1<='1'; WAIT FOR CLK_P;

-- code that executes only once

END PROCESS ;
A1<="1111000011110000","0000111100001111"AFTER 1000 NS,"1111000000001111"AFTER 2000 NS,"1111000011110000"AFTER 3000 NS;
B1<="1111000011110000","0000111100001111"AFTER 1000 NS,"1111000000001111"AFTER 2000 NS,"1111000011110000"AFTER 3000 NS;

END ADDER16B_arch;