entity fenpin2 is port(
clk: in std_logic;
reset: in std_logic; clkfenpin2: out std_logic
);
end fenpin2;
architecture behavioral of fenpin2 is signal clktmp:std_logic;
begin
process(clk,reset) begin
if(reset='1') then clktmp<='0';
elsif(clk'event and clk='1') then clktmp<=not clktmp;
end if; end process;
clkfenpin2<=clktmp; end behavioral;
entity count16 is port(clkfenpin2 :in STD_LOGIC;
reset :in STD_LOGIC;
w :in STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END count16;
architecture Behavioral of count16 is
signal Y:STD_LOGIC_VECTOR(3 DOWNTO 0)); begin
process(clk,reset) begin
if rising_edge(clk)then IF reset='1' then
Q<="0000" ELSE
Q<=Y; end if;
end if; end process;
Y(0)<=(not(w) and Q(0))or (w and not(Q(0)));
Y(1)<=(not(w) and Q(1))or (w and Q(1) and not(Q(0)))or(w and not(Q(1))and Q(0));
Y(2)<=(w and Q(2) and not (Q(0))) or (w and not Q(2)) or (w not(Q(2)) and Q(1) and Q(0)) or (w and Q(2) and not(Q(1)));
Y(3)<=(not(w) and Q(3)) or (w and Q(3) and not(Q(0))) or (w and not(Q(3)) and Q(2) and Q(1) and Q(0)) or (w and Q(3) and not(Q(2))) or (w and Q(3) and not(Q(1)));
end behavioral;