Verilog HDL

 ###### HDL刷题中通过实例化100个全加器创建100位二进制波纹进位加法器

 ###### 
``

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    integer i;
    always @(*)
        adder1 u0 (.a(a[0]),.b(b[0]),.cin(cin),.cout(cout[0]),.sum(sum[0]));
        begin
            for(i=1;i<100;i=i+1)
              
         adder1 ui (.a(a[i]),.b(b[i]),.cin(cout[i-1]),.cout(cout[i]),.sum(sum[i]));
        end
                

endmodule
module adder1( input a, b, cin,
             output cout,
             output [1:0]sum );
    reg [1:0]c1;
    assign c1=a+b+cin;
    assign sum=c1[0];
    assign cin=c1[1];
endmodule

```

 ###### Error (10170): Verilog HDL syntax error at top_module.v(8) near text: "u0"; expecting "<=", or "=", or "+=", or "-=", or "*=", or "/=", or "%=", or "&=", or "|=", or "^=", or "<<=", or ">>=", or "<<<=", or ">>>=", or "++", or "--". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.12035762/top_module.v Line: 8
Error (10170): Verilog HDL syntax error at top_module.v(9) near text: "begin"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.12035762/top_module.v Line: 9
Error (10112): Ignored design unit "top_module" at top_module.v(1) due to previous errors File: /home/h/work/hdlbits.12035762/top_module.v Line: 1
Error (10112): Ignored design unit "adder1" at top_module.v(17) due to previous errors File: /home/h/work/hdlbits.12035762/top_module.v Line: 17

 ###### 我的解答思路和尝试过的方法

 ###### 为什么出错

always 下不能例化

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    integer i;
        adder1 u0 (.a(a[0]),.b(b[0]),.cin(cin),.cout(cout[0]),.sum(sum[0]));
        for(i=1;i<100;i=i+1)
        begin:for_ix
            adder1 ui (.a(a[i]),.b(b[i]),.cin(cout[i-1]),.cout(cout[i]),.sum(sum[i]));
        end
               
 
endmodule
module adder1( input a, b, cin,
             output cout,
             output [1:0]sum );
    reg [1:0]c1;
    assign c1=a+b+cin;
    assign sum=c1[0];
    assign cin=c1[1];
endmodule