如何用Verilog在FPGA板上实现用key1和key2分别控制流向不同的4个led组成的间隔1s的流水灯？

麻烦各位帮忙看看问题出在哪里，我写出来只亮b0001

`timescale 1ns / 1ps

module jfbka(
    input sysclk,
    input rst_n,
    input key1,
    input key2,
    output reg [3:0] led
);

parameter delay = 500000;
parameter delay1 = 50000000;

reg [26:0] cnt1;
reg [26:0] cnt2; // key1和key2的消抖计时
reg [1:0] wa;
reg [26:0] cnt3; // key1和key2的流水计时
wire key1_flag;
wire key2_flag; // 按键指令

// 消抖程序
always@(posedge sysclk)
  begin
        if(!rst_n)
        begin
             cnt1<=0;
             cnt2<=0;
        end
        else if(key1==0)
            if(cnt1==delay-1)
                     cnt1<=cnt1;
            else
                     cnt1<=cnt1+1;                     
         else if(key2==0)
            if(cnt2==delay-1)
                    cnt2<=cnt2;
            else
                    cnt2<=cnt2+1;
        else
        begin
             cnt1<=0; 
             cnt2<=0; 
         end
    end

// 流水计时器
always @(posedge sysclk ) begin
    if (!rst_n)
        cnt3 <= 0;
    else if (cnt3 == delay1 - 1)
        cnt3 <= 0;
    else
        cnt3 <= cnt3 + 1;
end
 
// 流水程序
assign key1_flag = (cnt1 == delay - 2) ? 1 : 0;
assign key2_flag = (cnt2 == delay - 2) ? 1 : 0;
always @(posedge sysclk)begin
if(!rst_n)
wa<=0;
else if(key1_flag==1)
  wa<=1;
  else if(key2_flag==1)
  wa<=2;
  else
  wa<=wa;
  end
always @(posedge sysclk) begin
    if (!rst_n)
        led <= 4'b0001;
    else 
        case(wa)
            0:led=4'b0001;
            1: begin
                if(cnt3 == delay1-1)
                    led <= {led[2:0], led[3]};
                else
                    led <= led;
            end
            2: begin
                if(cnt3 == delay1-1)
                    led <= {led[0], led[3:1]};
                else
                    led <= led; 
            end     
            default: led <=4'b0001 ;
        endcase
    end   
   

    
endmodule

代码逻辑上毛病不少
1：cnt3,cnt4没赋值，没变化
2：key1_flag ，key2_flag ，wa 的逻辑也有问题
3：cnt1，cnt2 的计数也不对
需要大改