verilog序列检测模块

a为输入端，b为输出端，如果a连续输入为1101则b输出为1，否则为0。
例如a：0001100110110100100110
b：0000000000100100000000
请画出state machine；请用RTL描述其state machine。

module detection_1101
(
    input    rst_n,
    input    clk,
    input    a,
    output    b
);

reg        [3:0]    xbuf_r = 4'b0;

assign    b    = {xbuf_r[2:0],a} == 4'b1101 ? 1:0;

always@(posedge clk)
begin
    if(rst_n == 0)
        xbuf_r    <= 4'b0;
    else
        xbuf_r    <= {xbuf_r[2:0],a};
end

endmodule