VHDL一直报错
报错如下
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Mon Jun 05 20:20:32 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off num_display -c num_display
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Error (10500): VHDL syntax error at num_display.vhd(50) near text "function"; expecting "end", or "(", or an identifier ("function" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at num_display.vhd(50) near text ":"; expecting ")", or ","
Error (10500): VHDL syntax error at num_display.vhd(53) near text "function"; expecting ";", or an identifier ("function" is a reserved keyword), or "architecture"
Info (12021): Found 0 design units, including 0 entities, in source file num_display.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 4654 megabytes
Error: Processing ended: Mon Jun 05 20:20:33 2023
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings
以下是代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity num_display is
port (
clk : in std_logic;
sw : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(7 downto 0);
sel : out std_logic_vector(7 downto 0)
);
end num_display;
architecture Behavioral of num_display is
signal counter : integer range 0 to 3999 := 0;
signal disp_val : std_logic_vector(7 downto 0) := "11111111";
signal disp_sel : std_logic_vector(7 downto 0) := "11111110";
-- 数字对应的七段码
constant SEGMENTS : std_logic_vector(15 downto 0) := "0000000000111111" & -- 0
"0000000000000110" & -- 1
"0000000001011011" & -- 2
"0000000001001111" & -- 3
"0000000001100110" & -- 4
"0000000001101101" & -- 5
"0000000001111101" & -- 6
"0000000000000111" & -- 7
"0000000001111111" & -- 8
"0000000001101111" & -- 9
"0000000001110111" & -- A
"0000000001111100" & -- b
"0000000000111001" & -- C
"0000000001011110" & -- d
"0000000001111001" & -- E
"0000000001110001"; -- F
begin
-- 计数器，用于控制数码管的动态显示
process(clk)
begin
if rising_edge(clk) then
counter <= counter + 1;
if counter = 4000 then
counter <= 0;
end if;
end if;
end process;
-- 数字转七段码
function to_segment(value : integer) return std_logic_vector is
begin
return SEGMENTS(value);
end function;
-- 选择要显示的数码管和段
disp_sel_proc : process(counter)
begin
case counter is
when 0 =>
disp_sel <= "11111110";
disp_val <= to_segment(to_integer(unsigned(sw)));
when 1000 =>
disp_sel <= "11111101";
disp_val <= to_segment(to_integer(unsigned(sw)) / 16);
when 2000 =>
disp_sel <= "11111011";
disp_val <= to_segment(to_integer(unsigned(sw)) / 256);
when 3000 =>
disp_sel <= "11110111";
disp_val <= to_segment(to_integer(unsigned(sw)) / 4096);
when others =>
disp_sel <= "11111111";
disp_val <= "11111111";
end case;
end process;
-- 输出段选和位选信号
seg <= disp_val;
sel <= disp_sel;
end Behavioral;
从Quartus II的输出日志中可以看出，代码中存在一些语法错误，导致编译失败。
在你提供的错误信息中，有三个错误被列出：
VHDL语法错误，在 num_display.vhd 文件的第50行，有一个“function”保留字被误用。检查该行并确保语法正确，并且不存在其他语法错误。
在第50行后面的位置，一个分号“;”或一个逗号“,”错误地放在了冒号后面。这个错误也需要检查并纠正。
在 num_display.vhd 文件的第53行，存在某个不能识别的保留字“function”错误。该错误也需要检查并纠正。
建议你仔细检查代码中的这些错误，确保语法正确。另外，你可以尝试使用VHDL语言编辑器来检查和修复语法错误。例如，在Quartus II中可以使用VHDL的“Manual HDL Editing”功能来快速检查和修复语法错误。