汽车车灯控制系统，报错修改

用verilog hdl 设计一个汽车车灯控制系统具体要求如下：

以下是设计：

module car_lights(
    input clk, // 时钟信号
    input reset, // 复位信号
    input day_light, // 日间行车灯开关信号
    input right_turn, // 右转灯开关信号
    input left_turn, // 左转灯开关信号
    input brake, // 刹车灯开关信号
    input fault, // 故障指示灯开关信号
    output reg car_light, // 行车灯控制信号
    output reg right_light, // 右转灯控制信号
    output reg left_light, // 左转灯控制信号
    output reg brake_light, // 刹车灯控制信号
    output reg fault_light // 故障指示灯控制信号
);

reg [1:0] state; // 状态寄存器
reg [3:0] count; // 计数器
reg cp; // CP信号

// 状态定义
parameter S_IDLE = 2'b00;
parameter S_RIGHT = 2'b01;
parameter S_LEFT = 2'b10;
parameter S_BRAKE = 2'b11;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        state <= S_IDLE;
        count <= 4'd0;
        cp <= 1'b0;
        car_light <= 1'b0;
        right_light <= 1'b0;
        left_light <= 1'b0;
        brake_light <= 1'b0;
        fault_light <= fault;
    end else begin
        case (state)
            S_IDLE: begin
                if (day_light) begin
                    car_light <= 1'b1;
                end else begin
                    car_light <= 1'b0;
                end
                right_light <= 1'b0;
                left_light <= 1'b0;
                brake_light <= brake;
                fault_light <= fault;
                if (right_turn) begin
                    state <= S_RIGHT;
                    count <= 4'd0;
                end else if (left_turn) begin
                    state <= S_LEFT;
                    count <= 4'd0;
                end else if (brake) begin
                    state <= S_BRAKE;
                    count <= 4'd0;
                end else begin
                    state <= S_IDLE;
                    count <= 4'd0;
                end
            end
            S_RIGHT: begin
                if (day_light) begin
                    car_light <= 1'b1;
                end else begin
                    car_light <= 1'b0;
                end
                right_light <= count[1];
                left_light <= 1'b0;
                brake_light <= cp;
                fault_light <= fault;
                count <= count + 1;
                if (count == 4'd3) begin
                    count <= 4'd0;
                end
                if (!right_turn) begin
                    state <= S_IDLE;
                    count <= 4'd0;
                end
            end
            S_LEFT: begin
                if (day_light) begin
                    car_light <= 1'b1;
                end else begin
                    car_light <= 1'b0;
                end
                right_light <= 1'b0;
                left_light <= count[1];
                brake_light <= cp;
                fault_light <= fault;
                count <= count + 1;
                if (count == 4'd3) begin
                    count <= 4'd0;
                end
                if (!left_turn) begin
                    state <= S_IDLE;
                    count <= 4'd0;
                end
            end
            S_BRAKE: begin
                if (day_light) begin
                    car_light <= 1'b1;
                end else begin
                    car_light <= 1'b0;
                end
                right_light <= 1'b0;
                left_light <= 1'b0;
                brake_light <= cp;
                fault_light <= fault;
                count <= count + 1;
                if (count == 4'd3) begin
                    count <= 4'd0;
                end
                if (!brake) begin
                    state <= S_IDLE;
                    count <= 4'd0;
                end
            end
        endcase
    end
end

always @(posedge clk ) begin
    if (reset) begin
        cp <= 1'b0;
    end else begin
        cp <= ~cp;
    end
end

endmodule

具体报错如下：

该如何修改啊，请各位帮忙指正一下，非常感谢

把图片中的这一行代码删除掉