[DRC 23-20] Rule violation (PLIDC-7)

vivado 2015.2综合过了，但是编译报错：
[DRC 23-20] Rule violation (PLIDC-7)[DRC 23-20] Rule violation (PLIDC-7) IDELAYCTRL DRC Checks - Design has more than one unlocked and ungrouped IDELAYCTRL instances. Please instantiate a delay controller (or use an existing one if delay values allow so) and apply appropriate IODELAY_GROUP or LOC constraints on the delay instances, or instantiate only one delay controller for the design without any IODELAY_GROUP or LOC constraints. The instances involved are:

U0_IDELAYCTRL

U1_IDELAYCTRL

这个错误信息指的是你的FPGA设计中存在IDELAYCTRL实例的放置问题。具体来说，在设计中存在多个未锁定和未分组的IDELAYCTRL实例，应该只实例化一个延迟控制器（或使用现有的延迟值允许的延迟控制器）并在延迟实例上应用适当的IODELAY_GROUP或LOC约束。相关实例是UO_IDELAYCTRL和U1_IDELAYCTRL。