用D触发器构成按循环码规律工作的六进制同步计数器

用D触发器构成按循环码(000 001 011 111 101 100 000)规律工作的六进制同步计数器，用Verilog实现，请求帮助！

module cntx
(
    input            clk,
    output    [2:0]    cnt
);
reg    [2:0]    cnt_r    = 0;
assign        cnt        = cnt_r;
always @(posedge clk)
begin
    case(cnt_r)
    3'b000:    cnt_r    <= 3'b001;
    3'b001:    cnt_r    <= 3'b011;
    3'b011:    cnt_r    <= 3'b111;
    3'b111:    cnt_r    <= 3'b101;
    3'b101:    cnt_r    <= 3'b100;
    3'b100:    cnt_r    <= 3'b000;
    default:cnt_r    <= 3'b000;
    endcase
end
endmodule