Errors: 0, Warnings: 0
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneiv_hssi_ver -L cycloneiv_pcie_hip_ver -L cycloneiv_ver -L rtl_work -L work -voptargs="+acc" tb_crc
Error loading design
Error: Error loading design
Pausing macro execution
MACRO ./crc_8_run_msim_rtl_verilog.do PAUSED at line 48
questasim仿真出现这个提示,没有问题也没有警告,但是出不了波形