//digit 当前带显示的数字
reg [3:0]digit;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
digit=4'd0;
else
case(bitcnt)
2'd0:digit=x[3:0];
2'd1:digit=x[7:4];
2'd2:digit=x[11:8];
2'd3:digit=x[15:12];
default:digit=4'd0;
endcase
end
//a_to_g;段码信号,共阴极数码管,段码高有效
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
a_to_g=7'b1111111;
else
case(digit)
0:a_to_g=7'b1111110;
1:a_to_g=7'b0111101;
2:a_to_g=7'b1101101;
3:a_to_g=7'b1111001;
4:a_to_g=7'b0110011;
5:a_to_g=7'b1011011;
6:a_to_g=7'b1011111;
7:a_to_g=7'b1110000;
8:a_to_g=7'b1111111;
9:a_to_g=7'b1111011;
default:a_to_g=7'b1111110;
endcase
end
endmodule
module xuehao(
input clk,
input rst_n,
output reg [13:0] a_to_g,
output reg [7:0] an
);
wire [15:0] ax=16'b0001_1001_0010_0000;
wire [15:0] bx=16'b0000_0100_0011_0110;
wire [6:0] aa_to_g;
wire [6:0] ba_to_g;
wire [3:0] aan;
wire [3:0] ban;
display_id zhuozhuo1(
.clk(clk),
.rst_n(rst_n),
.x(ax),
.a_to_g(aa_to_g),
.an(aan)
);
display_id zhuozhuo2(
.clk(clk),
.rst_n(rst_n),
.x(bx),
.a_to_g(ba_to_g),
.an(ban)
);
always @*
begin
a_to_g={aa_to_g,ba_to_g};
an={aan,ban};
end
endmodule
将你的堵塞赋值更改为非堵塞
代码没经过验证,不见的正确,需要你自己去调试
//输出需要加个小数点,数码管小数点的管脚一般是 dp
//输入需要加4位小数点,决定这个模块对应的小数点是否显示。 dot[3:0] 对应的 1 显示点,0 不显示
module display_id
(
input clk,
input rst_n,
input [3:0] dot, //输入1111 4个小数点都亮,0001 显示第一个小数点
input [15:0] x, //等待显示的BCD码
output reg [6:0] a_to_g, //段信号
output reg dp, //小数点
output reg [3:0] an //位选信号
);
reg [20:0] clkdiv;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
clkdiv<=21'd0;
else
clkdiv<=clkdiv+1;
end
//bitcnt:位扫描信号 0~1循环变化 扫描周期5.24ms 控制总扫描时间不超过10ms,单个数码管显示时间约为5ms
wire [1:0]bitcnt;
assign bitcnt=clkdiv[20:19];
//an:位选信号产生,高有效
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
an<=4'd0;
else
case(bitcnt)
2'd0:an<=4'b0001;
2'd1:an<=4'b0010;
2'd2:an<=4'b0100;
2'd3:an<=4'b1000;
endcase
end
//digit 当前带显示的数字
reg [3:0]digit;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
digit<=4'd0;
else
case(bitcnt)
2'd0:digit<=x[3:0];
2'd1:digit<=x[7:4];
2'd2:digit<=x[11:8];
2'd3:digit<=x[15:12];
default:digit<=4'd0;
endcase
end
//a_to_g;段码信号,共阴极数码管,段码高有效
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
a_to_g<=7'b1111111;
dp <= 0;
end
else
begin
dp <= dot[bitcnt];
case(digit)
0:a_to_g<=7'b1111110;
1:a_to_g<=7'b0111101;
2:a_to_g<=7'b1101101;
3:a_to_g<=7'b1111001;
4:a_to_g<=7'b0110011;
5:a_to_g<=7'b1011011;
6:a_to_g<=7'b1011111;
7:a_to_g<=7'b1110000;
8:a_to_g<=7'b1111111;
9:a_to_g<=7'b1111011;
default:a_to_g<=7'b1111110;
endcase
end
end
endmodule
module xuehao(
input clk,
input rst_n,
output reg [13:0] a_to_g,
output dp_a,//前4位小数点
output dp_b,//后4位小数点
output reg [7:0] an
);
wire [15:0] ax=16'b0001_1001_0010_0000;
wire [15:0] bx=16'b0000_0100_0011_0110;
wire [3:0] dot_a=4'b0001; //前4位数最后一个加小数点
wire [3:0] dot_b=4'b0000;
wire [6:0] aa_to_g;
wire [6:0] ba_to_g;
wire [3:0] aan;
wire [3:0] ban;
display_id zhuozhuo1(
.clk(clk),
.rst_n(rst_n),
.dot(dot_a),
.x(ax),
.a_to_g(aa_to_g),
.dp(dp_a),
.an(aan)
);
display_id zhuozhuo2(
.clk(clk),
.rst_n(rst_n),
.dot(dot_b),
.x(bx),
.a_to_g(ba_to_g),
.dp(dp_b),
.an(ban)
);
always @*
begin
a_to_g={aa_to_g,ba_to_g};
an={aan,ban};
end
endmodule