用hdl文件写两个16位2进制数字的除法

哪位精英人士可以写啊？
只能使用hdl文件
写出两个216位进制数字的除法
就只能用基本的逻辑门
And or not mux
Add subtract

试下下面这个

module divisionV1  
(  
input[31:0] a,   
input[31:0] b,  
input enable,
output reg [31:0] yshang,  
output reg [31:0] yyushu,
output reg done 
);  
  
reg[31:0] tempa;  
reg[31:0] tempb;  
reg[63:0] temp_a;  
reg[63:0] temp_b;  
  
integer i;  
  
always @(a or b)  
begin  
    tempa <= a;  
    tempb <= b;  
end  
  
always @(tempa or tempb)  
begin  
if(enable)
  begin
    temp_a = {32'h00000000,tempa};  
    temp_b = {tempb,32'h00000000};  
    done = 0; 
    for(i = 0;i < 32;i = i + 1)  
        begin  
            temp_a = {temp_a[62:0],1'b0};  
            if(temp_a[63:32] >= tempb)  
                temp_a = temp_a - temp_b + 1'b1;  
            else  
                temp_a = temp_a;  
        end  
  
    yshang = temp_a[31:0];  
    yyushu = temp_a[63:32]; 
    done = 1; 
  end
end  
  
endmodule

提供参考实例【VerilogHDL实现除法操作】，链接：https://blog.csdn.net/little_ox/article/details/118083267

module divisionV1  
(  
input[31:0] a,   
input[31:0] b,  
input enable,
output reg [31:0] yshang,  
output reg [31:0] yyushu,
output reg done 
);  
  
reg[31:0] tempa;  
reg[31:0] tempb;  
reg[63:0] temp_a;  
reg[63:0] temp_b;  
  
integer i;  
  
always @(a or b)  
begin  
    tempa <= a;  
    tempb <= b;  
end  
  
always @(tempa or tempb)  
begin  
if(enable)
  begin
    temp_a = {32'h00000000,tempa};  
    temp_b = {tempb,32'h00000000};  
    done = 0; 
    for(i = 0;i < 32;i = i + 1)  
        begin  
            temp_a = {temp_a[62:0],1'b0};  
            if(temp_a[63:32] >= tempb)  
                temp_a = temp_a - temp_b + 1'b1;  
            else  
                temp_a = temp_a;  
        end  
  
    yshang = temp_a[31:0];  
    yyushu = temp_a[63:32]; 
    done = 1; 
  end
end  
  
endmodule

测试环节

module tb_division(); 
  
reg [31:0] a;  
reg [31:0] b; 
reg enable; 
wire [31:0] yshang;  
wire [31:0] yyushu;  
wire done;


divisionV1 U1  
(  
    .a (a),  
    .b (b),  
    .enable(enable), 
    .yshang (yshang),  
    .yyushu (yyushu),
    .done(done)  
);  

initial  
begin  
enable=1;
    #10 a = 443525;  
        b = 32;  
end  
 
endmodule

试试这个思路呢