Verilog描述，分别用if语句和条件操作语句完成表述

EDA给出Verilog描述，注意其中D触发器和锁存器的表述，分别用if语句和条件操作语句完成表述

module rtl_1    //RTL 1 图 5-36
(
    input            D,
    input            CLK,
    input            EN,
    input            SET,
    input            RESET,
    output    reg        Q
);

wire    set_q;

assign    set_q = SET & ~RESET;

always @(posedge CLK or posedge RESET)
begin
    if(RESET)
        Q    <= 0;
    else if(set_q == 1)
        Q    <= 1;
    else if(EN == 1)
        Q    <= D;
end
endmodule

module rtl_2    //RTL 2 图 5-37
(
    input            A,
    input            B,
    input            C,
    input            D,
    output            Y
);

wire    tp1;
wire    tp2;

assign    tp1    = A | B;
assign    tp2    = C & D;

assign    Y = tp1 == 0 ? A:(tp1^tp2);

endmodule

module rtl_3    //RTL 3 图 5-38
(
    input            D,
    input            CLK,
    input            RST,
    output    reg        Q,
    output    reg        DOUT
);

wire    sel;
assign    sel = RST == 0 ? D:0;

always @(posedge CLK)
begin
    Q    <= sel;
end

always @(posedge CLK)
begin
    DOUT    <= sel ^ D;
end
endmodule

module rtl_4    //RTL 4 图 5-39
(
    input            D,
    input            CLK,
    input            RST,
    input            EN,
    output            Q1,
    output    reg        Q
);

assign    Q1 = RST | ~(D & EN);

always @(posedge CLK or posedge RST)
begin
    if(RST == 1)
        Q    <= 0;
    else if(EN == 1)    //if 语句
        Q    <= D;
end

endmodule

module rtl_5
(
    input            D,
    input            CLK,
    input            RST,
    input            EN,
    output            Q1,
    output    reg        Q
);

assign    Q1 = RST | ~(D & EN);

always @(posedge CLK or posedge RST)
begin
    if(RST == 1)
        Q    <= 0;
    else
        Q    <= EN == 1 ? D:Q;    //条件语句
end

endmodule