Verilog仿真输出如何删除多余地址位

编写Verilog的时候（状态机），仿真输出led刚开始是00和01，理想效果是0和1
最开始的时候是这样

module LED(clk,rst_n,led);

    input clk;
    input rst_n;
    
    output reg  [1:0] led;

仿真输出的led是00和01
现在改了一下

module LED(clk,rst_n,led);

    input clk;
    input rst_n;
    
    output reg led;

这时候仿真的led直接变成z0和z1了，想问一下这个要怎么改
附仿真程序

`timescale 1ns/1ps
module LED_tb;

    reg clk;
    reg rst_n;
    wire led;
    
    parameter t = 5;
    parameter s1 = 10;
    parameter s2 = 20;
    LED #(.t(t),.s1(s1),.s2(s2)) 
        DUT(
        .clk(clk),
        .rst_n(rst_n),
        .led(led)
        );
    
    initial begin
    clk = 0;
    rst_n = 0;
    
    #200
    rst_n = 1;
    
    #5000
    $stop;
    end
    
    always #10 clk = ~clk;

endmodule

程序本体是这样

module LED(clk,rst_n,led);

    input clk;
    input rst_n;
    
    output reg [1:0] led;
    
    reg [31:0] cnt1;
    reg [31:0] cnt2;
    reg [31:0] cnt3;
    reg x1;
    reg x2;
    parameter t = 50_000_000;
    parameter s1 = 100_000_000;
    parameter s2 = 200_000_000;
    always @(posedge clk,negedge rst_n)begin
    if(!rst_n)
        cnt1 <= 0;
    else
        if(cnt1 < t - 1||x1 == 0)
            cnt1 <= cnt1 + 1;
        else
            cnt1 <= 0;
            x1 <= 1;
    if(!rst_n)
        cnt2 <= 0;
    else
        if(cnt2 < s1 - 1||x1 == 1||x2 == 0)
            cnt2 <= cnt2 + 1;
        else
            cnt2 <= 0;
            x2 <= 1;
    if(!rst_n)
        cnt3 <= 0;
    else
        if(cnt3 < s2 - 1||x2 == 1)
            cnt3 <= cnt3 + 1;
        else
            cnt3 <= 0;
    end
    
    wire flag1;
    wire flag2;
    wire flag3;

    assign flag1 = (cnt1 == t - 1)?1'b1:1'b0;
    assign flag2 = (cnt2 == s1 - 1 )?1'b1:1'b0;
    assign flag3 = (cnt3 == s2 - 1 )?1'b1:1'b0;
    
    reg [1:0] state;
    
    parameter s00 = 2'b00;
    parameter s01 = 2'b01;
    parameter s02 = 2'b10;
    
    always @(posedge clk,negedge rst_n)begin
    if( rst_n==0 )
        begin
            state <= s01;
            led <= 1'b1;
        end
    else
            case(state)
                s00:begin
                        led <= 1'b1;
                        if (flag2 == 1'b1)
                            state <= s01;
                        else 
                            state <= s00;
                     end
                s01:begin
                        led<= 1'b0;
                        if (flag3 == 1'b1)
                        state <= s02;
                        else
                        state <= s01;
                     end
                s02:begin
                        led<=1'b1;
                     end
            endcase
    end
endmodule

想问一下要怎么去修改

有些不太理解你的问题
你这么改 led 能的到 0和1 ,不会出现 z0 和 z1
把你的仿真图贴出来

module LED(clk,rst_n,led);
 
    input clk;
    input rst_n;
    
    output reg led;