verilog HDL8位流水灯

verilog HDL 程序编写，时间间隔一秒，8个指示灯依次亮灭。

module led_mx
(
    input    clk,
    input    rst_n,
    output    reg[7:0]    led//读数据
);

parameter    CNTS = 100_000_000;    //假设时钟 100MHz 计数 1 秒
reg    [31:0]    clk_cnt;
reg            clk_s;

//产生秒脉冲 clk_s
always @(posedge clk) begin
    if( rst_n == 0 )begin
        clk_cnt <= 32'd0;
        clk_s    <= 1'd0;
    end
    else if(clk_cnt < CNTS -1) begin
        clk_cnt    <= clk_cnt + 1'd1;
        clk_s    <= 1'd0;
    end
    else begin
        clk_cnt <= 32'd0;
        clk_s    <= 1'd1;
    end
end


always @(posedge clk) begin
    if( rst_n == 0 )
        led <= 8'b0000_0001;
    else if(clk_s == 1)
        led    <= {led[6:0],led[7]};
end

endmodule