vivado如下报错

[Synth 8-448] named port connection 'clk_72MHz_out' does not exist for instance 'instance_of_clk_wiz_0' of module 'clk_wiz_0' ["C:/Users/22872/Desktop/pri_uart_release/source/verilog/top_module.v":63]
这个要怎么解决呢

clk_wiz_0 应该是ip核，你确认一下这个ip核是否有clk_72Mhz 这个端口。实例化时建议你直接拷贝ip核的实例化模板，这样不容易出错

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