Determine whether the statement is true or false and explain why.

a. FPGAs with more CLBs are generally more expensive.
b. To design with minimized hardware, behavioral description is convenient.
c. “For loop” can be used only in an always block (behavioral descriptions).
d. Verilog modules developed with Xilinx systems cannot be used directly on
Altera systems.
e. Simulation for FPGA should start from smaller components and then larger ones.