vhdl的component 错误

VHDL 问题

部分代码

component debounce1 is
PORT MAP (
clk => clk,
rst => rst,
key => BTN7,
key_pulse1 => key_pulse1
);
end component debounce1;

component debounce2 is
PORT MAP (
clk => clk,
rst => rst,
key => BTN6,
key_pulse2 => key_pulse2
);
end component debounce2;

component debounce3 is
PORT MAP (
clk => clk,
rst => rst,
key => BTN5,
key_pulse3 => key_pulse3
);

component debounce4 is
PORT MAP (
clk => clk,
rst => rst,
key => BTN3,
key_pulse4 => key_pulse4
);
end component debounce4;

请问如何解决，谢谢

这个component有什么问题？