verilog状态发生了但begin里面的语句没有执行
图中的m状态发生转换了，但是a4没有赋值，door也没有变成1，本来按道理a和b2相等时，door应该为1；但是现在没有任何反应。
我赋了初值的
```c
module master_crl(door,up,down,a,b,up1,down1,b3,b1,b2,a3,a4,m);
input[3:0] a;
input[4:0] b;
output[2:0] up,down,up1,down1,m;
output[5:0] a3,b3,b1,b2,a4;
output door;
reg[2:0] up1,down1,down2,up2,up3,down,up;
reg door=0;
reg[5:0] b1,b2,b3,a3,a4;
reg[4:0] memory=5'd1;
reg[4:0] state;
integer i=0,j;
reg[2:0] k=0,l=0,o=0,flag; //sign of ask
reg[2:0] m=1,n=0;
parameter[4:0] wait1=0,wait2=1,wait3=0,wait4=1,state1=10;
function[4:0] abs;
input[4:0] x;
input[4:0] y;
if(x>y) abs=x-y;
else abs=y-x;
endfunction
//initial
// begin
// m=0;
// end
always@(a or b)
begin
up<=k*up1;
down<=l*down1;
case(b)
5'd0:b3<=5'd0;
5'd1:b3<=5'd1;
5'd2:b3<=5'd2;
5'd3:b3<=5'd3;
5'd4:b3<=5'd4;
5'd5:b3<=5'd5;
5'd6:b3<=5'd6;
5'd17:begin b1<=5'd1;b2<=5'd2;end
5'd18:begin b1<=5'd1;b2<=5'd3;end
5'd19:begin b1<=5'd1;b2<=5'd4;end
5'd20:begin b1<=5'd1;b2<=5'd5;end
5'd21:begin b1<=5'd1;b2<=5'd6;end
5'd22:begin b1<=5'd2;b2<=5'd3;end
5'd23:begin b1<=5'd2;b2<=5'd4;end
5'd24:begin b1<=5'd2;b2<=5'd5;end
5'd25:begin b1<=5'd2;b2<=5'd6;end
5'd26:begin b1<=5'd3;b2<=5'd4;end
5'd27:begin b1<=5'd3;b2<=5'd5;end
5'd28:begin b1<=5'd3;b2<=5'd6;end
5'd29:begin b1<=5'd4;b2<=5'd5;end
5'd30:begin b1<=5'd4;b2<=5'd6;end
5'd31:begin b1<=5'd5;b2<=5'd6;end
endcase
if((up1==0)&&(down1==0)) m<=wait1;
if((b<16)&&(b>0))
begin
if(a==b)
begin
for(j=0;j<5;j=j+1)begin door<=1;up1<=0;down1<=0;end
case(a)
5'b00001:a3<=5'b00001;
5'b00010:a3<=5'b00010;
5'b00011:a3<=5'b00011;
5'b00100:a3<=5'b00100;
5'b00101:a3<=5'b00101;
5'b00110:a3<=5'b00110;
endcase
end
if(a<b)
begin
k<=1;door<=0;
up1<=b-a3;
end
if(a>b)
begin
l<=1;door<=0;
down1<=a3-b;
end
end
else
begin
k<=1;l<=1;
case(a)
5'b00001:a3<=5'b00001;
5'b00010:a3<=5'b00010;
5'b00011:a3<=5'b00011;
5'b00100:a3<=5'b00100;
5'b00101:a3<=5'b00101;
5'b00110:a3<=5'b00110;
endcase
if(abs(b1,a3)>abs(b2,a3))
begin
case(m)
wait1:begin
if(a==b2)
begin
begin door<=1;up1<=0;down1<=0;end //open door 5s ask first
case(a3)
5'b00001:a4<=5'b00001;
5'b00010:a4<=5'b00010;
5'b00011:a4<=5'b00011;
5'b00100:a4<=5'b00100;
5'b00101:a4<=5'b00101;
5'b00110:a4<=5'b00110;
endcase
m<=wait2;
end
else if(a<b2)
begin
door<=0;up1<=b2-a3;down1<=0;flag<=1;
m<=wait1;
end
else
begin
door<=0;up1<=0;down1<=a3-b2;flag<=1;
m<=wait1;
end
end
wait2:begin
if(a==b1)
begin
begin door<=1;up1<=0;down1<=0;end //second
m<=wait1;
end
else if(a<b1)
begin
door<=0;up1<=b1-a4;down1<=0;
m<=wait2;
end
else
begin
door<=0;up1<=0;down1<=a4-b1;
m<=wait2;
end
end
endcase
end
// else
// begin
// case(n)
// wait3:begin
// if(a3<b1)
// begin
// begin door=0;up1<=b1-a3;down1<=0;end
// n=wait3;
// end
// else if(a3==b1)
// begin
// for(j=0;j<5;j=j+1)begin door=1;up1<=0;down1<=0;end //open door 5s ask first
// n=wait4;
// end
// else
// begin
// begin door=0;up1<=0;down1<=a3-b1;end
// n=wait3;
// end
// end
// wait4:begin
// if(a3<b2)
// begin
// begin door=0;up1<=b2-a3;down1<=0;end
// n=wait4;
// end
// else if(a3>b2)
// begin
// begin door=0;up1<=0;down1<=a3-b2;end
// n=wait4;
// end
// else
// begin
// for(j=0;j<5;j=j+1)begin door=1;up1<=0;down1<=0;end //second
// n=wait3;
// end
// end
// endcase
// end
end
end
endmodule
```
case(m)中的wait1可能不是转换之后的值，没有进入到wait1下的模块中去，语句没有被执行
case(m)的后面是写了wait1，wait2，wait3和wait4四种情况么？
如果四个都有的话，代码第15行，定义相等的状态可不行。
要学会在代码区里把代码贴全，别用图片。代码不全就只能猜测，不容易得到准确的答案
把这个begin end 删了试试，没用的
