vivado 2018上行为仿真已经通过了,但是综合后功能仿真出现高阻态,发现是system verilog代码状态机部分next_state变量出现问题,综合信息显示:
[Synth 8-5544] ROM "next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
我非常不理解为什么vivado尝试将我的状态机FSM映射到内存,导致该问题,请问如何解决?
部分代码如下:
localparam STATE_WIDTH=5;
localparam ILLEGAL_STATE=5'd0;
localparam IDLE_STATE=5'd1;
localparam WAIT_CONDITION0_STATE=5'd2;
localparam WAIT_CONDITION1_STATE=5'd4;
localparam LLR_START_READ_CAL_STORE_STATE=5'd8;
localparam LLR_READ_CAL_STORE_STATE=5'd16;
reg [STATE_WIDTH-1:0] current_state;
reg [STATE_WIDTH-1:0] next_state;
always_ff@(posedge clk or posedge reset)
begin
if(reset)
begin
current_state<=IDLE_STATE;
end
else
begin
current_state<=next_state;
end
end
//state judge
always_comb
begin
if(reset)
begin
next_state=IDLE_STATE;
end
else
begin
case(current_state)
IDLE_STATE:
begin
if(...)
begin
next_state=LLR_START_READ_CAL_STORE_STATE;
end
else if(...)
begin
next_state=WAIT_CONDITION1_STATE;
end
else if(...)
begin
next_state=WAIT_CONDITION0_STATE;
end
else
begin
next_state=IDLE_STATE;
end
end
WAIT_CONDITION1_STATE:
begin
if(...)
begin
next_state=LLR_START_READ_CAL_STORE_STATE;
end
else
begin
next_state=WAIT_CONDITION1_STATE;
end
end
WAIT_CONDITION0_STATE:
begin
if(...)
begin
next_state=LLR_START_READ_CAL_STORE_STATE;
end
else
begin
next_state=WAIT_CONDITION0_STATE;
end
end
LLR_START_READ_CAL_STORE_STATE:
begin
if(...)
begin
next_state=IDLE_STATE;
end
else if(...)
begin
next_state=LLR_READ_CAL_STORE_STATE;
end
else
begin
next_state=LLR_START_READ_CAL_STORE_STATE;
end
end
LLR_READ_CAL_STORE_STATE:
begin
if(...)
begin
next_state=IDLE_STATE;
end
else
begin
next_state=LLR_READ_CAL_STORE_STATE;
end
end
default:
begin
next_state=ILLEGAL_STATE;
end
endcase
end
end