情况

按照书上的例子使用quartus13.0进行时序仿真，无法正常输出波形。

电路图

波形图

报错

** Note: (vsim-3587) SDF Backannotation Successfully Completed.

Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst File: Block1.vt

** Error: d:/altera/13.0sp1/modelsim_ase/win32aloem/../altera/verilog/src/altera_primitives.v(289): $hold( posedge clk &&& nosloadsclr:2214 ps, d:2302 ps, 157 ps );

Time: 2302 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1/\inst1|11

** Error: d:/altera/13.0sp1/modelsim_ase/win32aloem/../altera/verilog/src/altera_primitives.v(289): $hold( posedge clk &&& nosloadsclr:2186 ps, d:2340 ps, 157 ps );

Time: 2340 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1/\inst|11

Simulation passed !

** Note: $finish : Block1.vt(149)

Time: 10 us Iteration: 0 Instance: /Block1_vlg_vec_tst/tb_out