Module parameter 'WRITE_GUARD' not found for override.

问题遇到的现象和发生背景

testbench文件，后仿真时出现这个问题
`timescale 1ns/1ns

`define DATA_WIDTH 8

`define STACK_WIDTH 3

module testbench;

reg clk ;

reg rst_n ;

reg wr_en ;

reg [`DATA_WIDTH-1:0] din ;

wire full ;

reg rd_en ;

wire [`DATA_WIDTH-1:0] dout ;

wire empty ;

// 鐢熸垚鏃堕挓

initial begin

clk = 0;

forever #5 clk = ~clk;

end

// Main

initial begin

rst_n = 0;

wr_en = 0;

din = 0;

rd_en = 0;

#50

rst_n = 1;

#50

repeat( 2**`STACK_WIDTH + 1 ) begin

@(posedge clk) begin

wr_en <= 1'b1;

din <= din + 1;

end

end

@(posedge clk)

wr_en <= 1'b0;

repeat( 2**`STACK_WIDTH + 1 ) begin

@(posedge clk) begin

rd_en <= 1'b1;

end

end

@(posedge clk)

rd_en <= 1'b0;

#50

repeat( 2**`STACK_WIDTH/2 ) begin

@(posedge clk) begin

wr_en <= 1'b1;

din <= din + 1;

end

end

@(posedge clk)

wr_en <= 1'b0;

#50

repeat( 2**`STACK_WIDTH/2 ) begin

@(posedge clk) begin

wr_en <= 1'b1;

din <= din + 1;

end

end

@(posedge clk)

wr_en <= 1'b0;

repeat( 2**`STACK_WIDTH/2 ) begin

@(posedge clk) begin

rd_en <= 1'b1;

end

end

@(posedge clk)

rd_en <= 1'b0;

#50

repeat( 2**`STACK_WIDTH/2 ) begin

@(posedge clk) begin

rd_en <= 1'b1;

end

end

@(posedge clk)

rd_en <= 1'b0;

#100

$stop;

end

Sync_Stack #(

.WRITE_GUARD("ON"),

.DATA_WIDTH (`DATA_WIDTH),

.STACK_WIDTH(`STACK_WIDTH)

) U_Sync_Stack (

.clk (clk),

.rst_n (rst_n),

.wr_en (wr_en),

.din (din),

.full (full),

.rd_en (rd_en),

.dout (dout),

.empty (empty)

);

endmodule

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运行结果及报错内容

我的解答思路和尝试过的方法

我想要达到的结果