Verilog -7到7的加、减、与、异或四种运算功能的运算器设计的代码是怎样设计的呢？

Verilog -7到7的加、减、与、异或四种运算功能的运算器设计的代码是怎样设计的呢？Verilog -7到7的加、减、与、异或四种运算功能的运算器设计的代码是怎样设计的呢？这代码实在不会，求大神指点。

module ALU_32(
    input [31:0] data_a_in,
    input [31:0] data_b_in,
    input carry_in,
    input [3:0] op_code,
    output reg carry_out,
    output reg [31:0] result_out
);

    localparam    ADD = 0, SUB = 1, AND = 2, OR = 3, XOR = 4, NONA = 5;
    
    always @ (op_code or data_a_in or data_b_in)
        case(op_code)
            ADD    :    {carry_out,result_out} <= data_a_in + data_b_in + carry_in;
            SUB    :    {carry_out,result_out} <= {data_a_in[31],data_a_in} - {data_b_in[31],data_b_in} - carry_in;
            AND    :    result_out <= data_a_in & data_b_in;
            OR        :    result_out <= data_a_in | data_b_in;            
            XOR    :    result_out <= data_a_in ^ data_b_in;
            NONA    :    result_out <= ~data_a_in;
            default    :    result_out <= data_a_in;
        endcase

endmodule 

localparam 表示运算类型(0-加法、1-减法、2-与、3-或、4异或、5取非)

module ALU_32(
input [31:0] data_a_in,
input [31:0] data_b_in,
input carry_in,
input [3:0] op_code,
output reg carry_out,
output reg [31:0] result_out
);
localparam ADD = 0, SUB = 1, AND = 2, OR = 3, XOR = 4, NONA = 5;
always @ (op_code or data_a_in or data_b_in)
case(op_code)
ADD : {carry_out,result_out} <= data_a_in + data_b_in + carry_in;
SUB : {carry_out,result_out} <= {data_a_in[31],data_a_in} - {data_b_in[31],data_b_in} - carry_in;
AND : result_out <= data_a_in & data_b_in;
OR : result_out <= data_a_in | data_b_in;
XOR : result_out <= data_a_in ^ data_b_in;
NONA : result_out <= ~data_a_in;
default : result_out <= data_a_in;
endcase
endmodule

Verilog是什么软件

没跑起来