Verilog语言Quartus II软件写cpu，在control模块里怎样初始化alus？总出现错误Error (10170): Verilog HDL

//alus初始化为x，加上将alus初 始化为x的语句，后续根据不同指令为alus赋值
//initial
begin
[3:0]alus<=4`b0000;
end
报这个错
Error (10170): Verilog HDL syntax error at control.v(129) near text "["; expecting "end"

alus[3:0]<=4`b0000;