verilog中的定义端口问题

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问题遇到的现象和发生背景 ：
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp27", which holds its previous value in one or more paths through the always construct

问题相关代码，请勿粘贴截图 ：module jt207jicunqi (sr9,sr8,sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0,zl,tmp10,tmp11,tmp12,tmp13,tmp14,tmp15,tmp16,tmp17,tmp20,tmp21,tmp22,tmp23,tmp24,tmp25,tmp26,tmp27,tmp30,tmp31,tmp32,tmp33,tmp34,tmp35,tmp36,tmp37,tmp40,tmp41,tmp42,tmp43,tmp44,tmp45,tmp46,tmp47); //sr:输入，zl：置零，js：计数
input sr9,sr8,sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0;
input zl;
output tmp10,tmp11,tmp12,tmp13,tmp14,tmp15,tmp16,tmp17,tmp20,tmp21,tmp22,tmp23,tmp24,tmp25,tmp26,tmp27;
output tmp30,tmp31,tmp32,tmp33,tmp34,tmp35,tmp36,tmp37,tmp40,tmp41,tmp42,tmp43,tmp44,tmp45,tmp46,tmp47;
reg tmp10,tmp11,tmp12,tmp13,tmp14,tmp15,tmp16,tmp17,tmp20,tmp21,tmp22,tmp23,tmp24,tmp25,tmp26,tmp27;
reg tmp30,tmp31,tmp32,tmp33,tmp34,tmp35,tmp36,tmp37,tmp40,tmp41,tmp42,tmp43,tmp44,tmp45,tmp46,tmp47;
always @(sr9 or sr8 or sr7 or sr6 or sr5 or sr4 or sr3 or sr2 or sr1 or sr0 or zl or tmp10 or tmp11 or tmp12 or tmp13 or tmp14 or tmp15 or tmp16 or tmp17 or tmp20 or tmp21 or tmp22 or tmp23 or tmp24 or tmp25 or tmp26 or tmp27 or tmp30 or tmp31 or tmp32 or tmp33 or tmp34 or tmp35 or tmp36 or tmp37 or tmp40 or tmp41 or tmp42 or tmp43 or tmp44 or tmp45 or tmp46 or tmp47)
begin
if(zl==1)begin
tmp10=0;tmp11=0;tmp12=0;tmp13=0;tmp14=0;tmp15=0;tmp16=0;tmp17=0;tmp20=0;tmp21=0;tmp22=0;tmp23=0;tmp24=0;tmp25=0;tmp26=0;tmp27=0;
tmp30=0;tmp31=0;tmp32=0;tmp33=0;tmp34=0;tmp35=0;tmp36=0;tmp37=0;tmp40=0;tmp41=0;tmp42=0;tmp43=0;tmp44=0;tmp45=0;tmp46=0;tmp47=0;
end
case({sr9,sr8,sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0})
10'b0000000001:
begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0000000010:
begin
tmp10 <= 1'b1;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0000000100:
begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b1;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0000001000:
begin
tmp10 <= 1'b1;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b1;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0000010000:
begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b1;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0000100000:
begin
tmp10 <= 1'b1;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b1;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0001000000:
begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b1;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b1;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0010000000:
begin
tmp10 <= 1'b1;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b1;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b1;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b0100000000:
begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b1;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
10'b1000000000:
begin
tmp10 <= 1'b1;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b1;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
default:begin
tmp10 <= 1'b0;
tmp11 <= tmp10;
tmp12 <= tmp11;
tmp13 <= tmp12;
tmp14 <= tmp13;
tmp15 <= tmp14;
tmp16 <= tmp15;
tmp17 <= tmp16;
tmp20 <= 1'b0;
tmp21 <= tmp20;
tmp22 <= tmp21;
tmp23 <= tmp22;
tmp24 <= tmp23;
tmp25 <= tmp24;
tmp26 <= tmp25;
tmp27 <= tmp26;
tmp30 <= 1'b0;
tmp31 <= tmp30;
tmp32 <= tmp31;
tmp33 <= tmp32;
tmp34 <= tmp33;
tmp35 <= tmp34;
tmp36 <= tmp35;
tmp37 <= tmp36;
tmp40 <= 1'b0;
tmp41 <= tmp40;
tmp42 <= tmp41;
tmp43 <= tmp42;
tmp44 <= tmp43;
tmp45 <= tmp44;
tmp46 <= tmp45;
tmp47 <= tmp46;
end
endcase
end
endmodule

运行结果及报错内容 ：Warning (12019): Can't analyze file -- file Verilog1.v is missing

Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp10", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp11", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp12", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp13", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp14", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp15", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp16", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp17", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp20", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp21", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp22", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp23", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp24", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp25", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp26", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp27", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp30", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp31", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp32", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp33", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp34", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp35", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp36", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp37", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp40", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp41", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp42", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp43", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp44", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp45", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp46", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at jt207jicunqi.v(8): inferring latch(es) for variable "tmp47", which holds its previous value in one or more paths through the always construct

我的解答思路和尝试过的方法 ：我有些看不懂报错的意思，有尝试修改，但越改越多。
我想要达到的结果：主要就是想实现一个0到9的十个按钮按下后，四条串行移位寄存器进行寄存。

case({sr9,sr8,sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0})
在这条语句前加个 else 改成这样就没 latch 的警告了
else case({sr9,sr8,sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0})
这代码用数组多好，能少10倍代码

代码太长，没法看。
你先将代码贴在代码区中