关于【Verilog】基于Nexys4DDR开发板实现数字钟中的问题

[Synth 8-3352] multi-driven net count[16] with 1st driver pin 'count_reg[16]/Q' ["C:/Users/lenovo/Desktop/project_final7/project_final7.srcs/sources_1/new/digital_clock.v":68]
[Synth 8-3352] multi-driven net count[16] with 2nd driver pin 'count_reg[16]__0/Q' ["C:/Users/lenovo/Desktop/project_final7/project_final7.srcs/sources_1/new/digital_clock.v":50]
关于您的【Verilog】基于Nexys4DDR开发板实现数字钟代码，我试了试，发现有这些错误，请问是为什呢。怎么改呢？