module seqdetb(input wire clk,input wire clr,input wire din,output reg dout ); reg [1:0] present_state,next_state; parameter S0= 3'b00,S1 = 3'b01,S2= 3'b10, S3= 3'b11; always @(posedge clk or posedge clr) begin if( clr== 1) present_state <= S0; else present_state<=next_state; end always@(*) begin case(present_state) S0: if(din== 1) next_state <= Sl; else next_state <= SO;S1: if(din== 1) next_state <= S2; else next_state <= S0;S2: if(din== 0) next_state <= S3; else next_state <= S2; S3: if(din== 1) next_state <= S1; else next_state = S0; default: next_state <= S0; endcase end always @( posedge clk or posedge clr)begin begin if(clr==l) dout <= 0; else if((present_state == S3) && (din==1)) dout<= l; else dout<= 0; end
endmodule关键出错在最后这边，提示syntax error near “endmoudule”其他地方应该是没错的，我也不知道这个错误怎么解决，希望有大神解答一下，谢谢