Quartus 告警10240Warning (10240): 解决

     always @(negedge rst or posedge bus_busy or negedge clk_without_dly_reg or posedge bus_idle)
     begin: proc_clk_cnt_gen
        if (rst == 1'b0)
           clk_cnt <= 0;
        else
           if (bus_busy == 1'b1)
           begin
              if (clk_without_dly_reg == 0)
                 clk_cnt <= clk_cnt + 1;
           end
           else if (bus_idle == 1'b1)
              clk_cnt <= 0;
     end

always @(negedge rst or posedge bus_busy or negedge clk_without_dly_reg or posedge bus_idle)
这么多时钟项，不行的
你得确定到底哪个是真正的时钟，可以再加上 rst 异步复位