testbench文件没问题，
报错如下

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L rtl_work -L work -voptargs="+acc" yima_tb

Error loading design

Error: Error loading design

Pausing macro execution

MACRO ./yima_run_msim_rtl_verilog.do PAUSED at line 12

怎么解决呢